Add support for linux+zephyr on rpi4

Signed-off-by: Yan-Jie Wang <[email protected]>

README.md

@@ -260,7 +260,7 @@ Build the firmware and deploy the system according to the target platform:
 | zcu104            | x         | x              |              |                  |
 | imx8qm            | x         | x              |              |                  |
 | tx2               | x         | x              |              |                  |
-| rpi4              | x         | x              |              |                  |
+| rpi4              | x         | x              | x            |                  |
 | qemu-aarch64-virt | x         | x              | x            |                  |
 | fvp-a-aarch64     | x         | x              | x            | x                |
 | fvp-a-aarch32     | x         | x              | x            | x                |

demos/linux+zephyr/configs/rpi4.c

@@ -0,0 +1,131 @@
+#include <config.h>
+
+VM_IMAGE(linux_image, XSTR(BAO_DEMOS_WRKDIR_IMGS/linux.bin));
+VM_IMAGE(zephyr_image, XSTR(BAO_DEMOS_WRKDIR_IMGS/zephyr.bin));
+
+struct config config = {
+
+    .shmemlist_size = 1,
+    .shmemlist = (struct shmem[]) {
+        [0] = { .size = 0x00010000, }
+    },
+
+    .vmlist_size = 2,
+    .vmlist = {
+        { 
+            .image = {
+                .base_addr = 0x20000000,
+                .load_addr = VM_IMAGE_OFFSET(linux_image),
+                .size = VM_IMAGE_SIZE(linux_image)
+            },
+
+            .entry = 0x20000000,
+
+            .platform = {
+                .cpu_num = 3,
+
+                .region_num = 1,
+                .regions =  (struct vm_mem_region[]) {
+                    {
+                        .base = 0x20000000,
+                        .size = 0x40000000,
+                        .place_phys = true,
+                        .phys = 0x20000000
+                    }
+                },
+
+               .ipc_num = 1,
+                .ipcs = (struct ipc[]) {
+                    {
+                        .base = 0xf0000000,
+                        .size = 0x00010000,
+                        .shmem_id = 0,
+                        .interrupt_num = 1,
+                        .interrupts = (irqid_t[]) {52}
+                    }
+                },
+
+                .dev_num = 2,
+                .devs =  (struct vm_dev_region[]) {
+                    {
+                        /* GENET */
+                        .pa = 0xfd580000,
+                        .va = 0xfd580000,
+                        .size = 0x10000,
+                        .interrupt_num = 2,
+                        .interrupts = (irqid_t[]) {189, 190}  
+                    },
+                    {   
+                        /* Arch timer interrupt */
+                        .interrupt_num = 1,
+                        .interrupts = 
+                            (irqid_t[]) {27}                         
+                    }
+                },
+
+                .arch = {
+                    .gic = {
+                        .gicd_addr = 0xff841000,
+                        .gicc_addr = 0xff842000,
+                    }
+                }
+            },
+        },
+        { 
+            .image = {  
+                .base_addr = 0x80000000,
+                .load_addr = VM_IMAGE_OFFSET(zephyr_image),
+                .size = VM_IMAGE_SIZE(zephyr_image)
+            },
+
+            .entry = 0x80000000,
+
+            .platform = {
+                .cpu_num = 1,
+
+                .region_num = 1,
+                .regions =  (struct vm_mem_region[]) {
+                    {   
+                        .base = 0x80000000,
+                        .size = 0x8000000 
+                    }
+                },
+
+                .ipc_num = 1,
+                .ipcs = (struct ipc[]) {
+                    {
+                        .base = 0x70000000,
+                        .size = 0x00004000,
+                        .shmem_id = 0,
+                        .interrupt_num = 1,
+                        .interrupts = (irqid_t[]) {52}
+                    }
+                },
+
+                .dev_num = 2,
+                .devs =  (struct vm_dev_region[]) {
+                    {   
+                        /* UART1 */
+                        .pa = 0xfe215000,
+                        .va = 0xfe215000,
+                        .size = 0x1000,
+                        .interrupt_num = 1,
+                        .interrupts = (irqid_t[]) {125}                        
+                    },
+                    {   
+                        /* Arch timer interrupt */
+                        .interrupt_num = 1,
+                        .interrupts = 
+                            (irqid_t[]) {27}                         
+                    }
+                },
+                .arch = {
+                    .gic = {
+                        .gicd_addr = 0xff841000,
+                        .gicc_addr = 0xff842000,
+                    }
+                }
+            },
+        },
+    },
+};

guests/zephyr/boards/arm64/baovm_rpi4/Kconfig.board

@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Carlo Caione <[email protected]>
+# Copyright (c) 2023 Yan-Jie Wang <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RASPBERRY_PI_4B
+	bool "Raspberry Pi 4B"
+	depends on SOC_BCM2711
+	select ARM64

guests/zephyr/boards/arm64/baovm_rpi4/Kconfig.defconfig

@@ -0,0 +1,13 @@
+# Copyright (c) 2019 Carlo Caione <[email protected]>
+# Copyright (c) 2023 Yan-Jie Wang <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_RASPBERRY_PI_4B
+
+config BUILD_OUTPUT_BIN
+	default y
+
+config BOARD
+	default "raspberry_pi_4b"
+
+endif # BOARD_RASPBERRY_PI_4B

guests/zephyr/boards/arm64/baovm_rpi4/baovm_rpi4.dts

@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2021 Carlo Caione <[email protected]>
+ * Copyright (c) 2023 Yan-Jie Wang <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Bao Raspberry Pi 4 Model B";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases { };
+
+	chosen {
+		/*
+		 * The SRAM node is actually located in the
+		 * DRAM region of the FVP Base RevC 2xAEMv8A.
+		 */
+		zephyr,sram = &dram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@ff841000 {
+			compatible = "arm,gic-v2", "arm,gic";
+			reg = <0xff841000 0x1000>,
+			      <0xff842000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		uart0: uart@fe215040 {
+			compatible = "brcm,bcm2711-aux-uart";
+			reg = <0xfe215040 0x40>;
+			clock-frequency = <500000000>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		dram0: memory@80000000 {
+			compatible = "mmio-sram";
+			reg = <0x80000000 DT_SIZE_M(128)>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+};

guests/zephyr/boards/arm64/baovm_rpi4/baovm_rpi4_defconfig

@@ -0,0 +1,12 @@
+CONFIG_SOC_BCM2711=y
+CONFIG_BOARD_RASPBERRY_PI_4B=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable serial port
+CONFIG_UART_INTERRUPT_DRIVEN=y