RISCy sim functions
#692
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RISCy sim functions
#692
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lmbollen
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hydrolarus
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Dec 4, 2024
| @@ -26,11 +28,34 @@ import Bittide.ProcessingElement | |||
| import Bittide.Wishbone | |||
| import Protocols.Idle | |||
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| -- Simulation imports | |||
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Maybe it's super overkill, but this sounds like LANGUAGE CPP could be nice for conditional imports and also later down in the file for the memory contents?
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I added two flags, one to include the binaries in the compilation named cpu-include-binaries, and sim-baud-rate that sets the baud rate to the maximum allowed by the domain for faster simulation.
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I know I'm on holiday 👀, but couldn't we use clashSimulation for this? CPP is somewhat terrible in the sense that it's very hard to keep all combinations of CPP compiling / testable.
`cpu-include-binaries` includes the corresponding riscv binary(if there is one) in the compilation process. This way we don't need to program the cpu over JTAG. `sim-baud-rate` sets the baud rate of the uart component to the maximum value allowed by its clock domain. This makes for faster simulation of softcore CPUs
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Debug some designs with a risc processor more easily by simulating it in your terminal