[Cider 2] First Pass Multi-component and Invokes

interp/cider2-tests/multi-comp/my_add.expect

@@ -0,0 +1,11 @@
+{
+  "left_reg": [
+    5
+  ],
+  "result": [
+    15
+  ],
+  "right_reg": [
+    10
+  ]
+}

interp/cider2-tests/multi-comp/my_add.futil

@@ -0,0 +1,64 @@
+import "primitives/core.futil";
+import "primitives/binary_operators.futil";
+
+component my_add(left: 32, right: 32) -> (out: 32) {
+    cells {
+        result = std_reg(32);
+        add = std_add(32);
+    }
+    wires {
+        group do_add {
+            add.left = left;
+            add.right = right;
+            result.in = add.out;
+            result.write_en = 1'd1;
+            do_add[done] = result.done;
+        }
+
+        out = result.out;
+    }
+
+    control {
+        do_add;
+    }
+}
+
+component main() -> () {
+    cells {
+        left_reg = std_reg(32);
+        right_reg = std_reg(32);
+        my_add = my_add();
+        result = std_reg(32);
+    }
+
+    wires {
+        group init_left {
+            left_reg.in = 32'd5;
+            left_reg.write_en = 1'd1;
+            init_left[done] = left_reg.done;
+        }
+
+        group init_right {
+            right_reg.in = 32'd10;
+            right_reg.write_en = 1'd1;
+            init_right[done] = right_reg.done;
+        }
+
+        group do_add {
+            my_add.go = 1'd1;
+            my_add.left = left_reg.out;
+            my_add.right = right_reg.out;
+            result.in = my_add.out;
+            result.write_en = my_add.done;
+            do_add[done] = result.done;
+        }
+    }
+
+    control {
+        seq {
+            init_left;
+            init_right;
+            do_add;
+        }
+    }
+}

interp/cider2-tests/multi-comp/my_add_invoke.expect

@@ -0,0 +1,11 @@
+{
+  "left_reg": [
+    5
+  ],
+  "result": [
+    15
+  ],
+  "right_reg": [
+    10
+  ]
+}

interp/cider2-tests/multi-comp/my_add_invoke.futil

@@ -0,0 +1,62 @@
+import "primitives/core.futil";
+import "primitives/binary_operators.futil";
+
+component my_add(left: 32, right: 32) -> (out: 32) {
+    cells {
+        result = std_reg(32);
+        add = std_add(32);
+    }
+    wires {
+        group do_add {
+            add.left = left;
+            add.right = right;
+            result.in = add.out;
+            result.write_en = 1'd1;
+            do_add[done] = result.done;
+        }
+
+        out = result.out;
+    }
+
+    control {
+        do_add;
+    }
+}
+
+component main() -> () {
+    cells {
+        left_reg = std_reg(32);
+        right_reg = std_reg(32);
+        my_add = my_add();
+        result = std_reg(32);
+    }
+
+    wires {
+        group init_left {
+            left_reg.in = 32'd5;
+            left_reg.write_en = 1'd1;
+            init_left[done] = left_reg.done;
+        }
+
+        group init_right {
+            right_reg.in = 32'd10;
+            right_reg.write_en = 1'd1;
+            init_right[done] = right_reg.done;
+        }
+
+        group store_result {
+            result.in = my_add.out;
+            result.write_en = 1'd1;
+            store_result[done] = result.done;
+        }
+    }
+
+    control {
+        seq {
+            init_left;
+            init_right;
+            invoke my_add(left=left_reg.out, right=right_reg.out)();
+            store_result;
+        }
+    }
+}

interp/cider2-tests/multi-comp/my_add_invoke_ref.expect

@@ -0,0 +1,11 @@
+{
+  "left_reg": [
+    5
+  ],
+  "result": [
+    15
+  ],
+  "right_reg": [
+    10
+  ]
+}

interp/cider2-tests/multi-comp/my_add_invoke_ref.futil

@@ -0,0 +1,63 @@
+import "primitives/core.futil";
+import "primitives/binary_operators.futil";
+
+component my_add(left: 32, right: 32) -> (out: 32) {
+    cells {
+        result = std_reg(32);
+        ref add = std_add(32);
+    }
+    wires {
+        group do_add {
+            add.left = left;
+            add.right = right;
+            result.in = add.out;
+            result.write_en = 1'd1;
+            do_add[done] = result.done;
+        }
+
+        out = result.out;
+    }
+
+    control {
+        do_add;
+    }
+}
+
+component main() -> () {
+    cells {
+        left_reg = std_reg(32);
+        right_reg = std_reg(32);
+        my_add = my_add();
+        result = std_reg(32);
+        inner_add = std_add(32);
+    }
+
+    wires {
+        group init_left {
+            left_reg.in = 32'd5;
+            left_reg.write_en = 1'd1;
+            init_left[done] = left_reg.done;
+        }
+
+        group init_right {
+            right_reg.in = 32'd10;
+            right_reg.write_en = 1'd1;
+            init_right[done] = right_reg.done;
+        }
+
+        group store_result {
+            result.in = my_add.out;
+            result.write_en = 1'd1;
+            store_result[done] = result.done;
+        }
+    }
+
+    control {
+        seq {
+            init_left;
+            init_right;
+            invoke my_add[add=inner_add](left=left_reg.out, right=right_reg.out)();
+            store_result;
+        }
+    }
+}

interp/cider2-tests/runt.toml

@@ -10,6 +10,14 @@ cmd = """
 timeout = 10
 expect_dir = "unit"
 
+[[tests]]
+name = "multi-comp"
+paths = ["multi-comp/*.futil"]
+cmd = """
+  ../../target/debug/cider {} -l ../../ flat --dump-registers | ../../target/debug/cider-data-converter --to json | jq --sort-keys
+"""
+timeout = 10
+
 # [[tests]]
 # name = "errors"
 # paths = ["tests/errors/*.futil"]
@@ -61,6 +69,7 @@ paths = ["../tests/control/invoke/*.futil"]
 cmd = """
 fud2 {} --from calyx --to dat --through interp-flat -s sim.data={}.data | jq --sort-keys
 """
+timeout = 10
 
 # [[tests]]
 # name = "invoke comp"

interp/src/flatten/flat_ir/base.rs

@@ -250,6 +250,50 @@ impl From<LocalCellOffset> for CellRef {
     }
 }
 
+#[derive(Debug)]
+pub enum GlobalCellRef {
+    Cell(GlobalCellIdx),
+    Ref(GlobalRefCellIdx),
+}
+
+impl From<GlobalRefCellIdx> for GlobalCellRef {
+    fn from(v: GlobalRefCellIdx) -> Self {
+        Self::Ref(v)
+    }
+}
+
+impl From<GlobalCellIdx> for GlobalCellRef {
+    fn from(v: GlobalCellIdx) -> Self {
+        Self::Cell(v)
+    }
+}
+
+impl GlobalCellRef {
+    pub fn from_local(local: CellRef, base_info: &BaseIndices) -> Self {
+        match local {
+            CellRef::Local(l) => (base_info + l).into(),
+            CellRef::Ref(r) => (base_info + r).into(),
+        }
+    }
+}
+
+pub enum CellDefinitionRef {
+    Local(CellDefinitionIdx),
+    Ref(RefCellDefinitionIdx),
+}
+
+impl From<RefCellDefinitionIdx> for CellDefinitionRef {
+    fn from(v: RefCellDefinitionIdx) -> Self {
+        Self::Ref(v)
+    }
+}
+
+impl From<CellDefinitionIdx> for CellDefinitionRef {
+    fn from(v: CellDefinitionIdx) -> Self {
+        Self::Local(v)
+    }
+}
+
 /// A global index for assignments in the IR
 #[derive(Debug, Eq, Copy, Clone, PartialEq, Hash, PartialOrd, Ord)]
 pub struct AssignmentIdx(u32);

interp/src/flatten/flat_ir/component.rs

@@ -63,6 +63,10 @@ pub struct ComponentCore {
     pub continuous_assignments: IndexRange<AssignmentIdx>,
     /// True iff component is combinational
     pub is_comb: bool,
+    /// The go port for this component
+    pub go: LocalPortOffset,
+    /// The done port for this component
+    pub done: LocalPortOffset,
 }
 
 #[derive(Debug, Clone)]
@@ -193,6 +197,13 @@ impl AuxillaryComponentInfo {
         self.cell_offset_map.skip(cell);
         self.ref_cell_offset_map.skip(ref_cell);
     }
+
+    pub fn get_cell_info_idx(&self, cell: CellRef) -> CellDefinitionRef {
+        match cell {
+            CellRef::Local(l) => self.cell_offset_map[l].into(),
+            CellRef::Ref(r) => self.ref_cell_offset_map[r].into(),
+        }
+    }
 }
 
 pub struct IdxSkipSizes {