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Fix tests in master branch #82

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Sep 5, 2024
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34 changes: 17 additions & 17 deletions examples/axi_lite_slave/tests/test_axi_lite_slave.py
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@


def setup_dut(dut):
cocotb.fork(Clock(dut.clk, CLK_PERIOD_NS, units='ns').start())
cocotb.start_soon(Clock(dut.clk, CLK_PERIOD_NS, units='ns').start())


# Write to address 0 and verify that value got through
Expand All @@ -27,12 +27,12 @@ async def write_address_0(dut):
"""

# Reset
dut.rst <= 1
dut.test_id <= 0
dut.rst.value = 1
dut.test_id.value = 0
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
setup_dut(dut)
await Timer(CLK_PERIOD_NS * 10, units='ns')
dut.rst <= 0
dut.rst.value = 0

ADDRESS = 0x00
DATA = 0xAB
Expand All @@ -59,17 +59,17 @@ async def read_address_4(dut):
The value read from the register is the same as the value written.
"""
# Reset
dut.rst <= 1
dut.test_id <= 1
dut.rst.value = 1
dut.test_id.value = 1
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
setup_dut(dut)
await Timer(CLK_PERIOD_NS * 10, units='ns')
dut.rst <= 0
dut.rst.value = 0
await Timer(CLK_PERIOD_NS, units='ns')
ADDRESS = 0x04
DATA = 0xCD

dut.dut.r_temp_1 <= DATA
dut.dut.r_temp_1.value = DATA
await Timer(CLK_PERIOD_NS * 10, units='ns')

value = await axim.read(ADDRESS)
Expand All @@ -92,12 +92,12 @@ async def write_and_read(dut):
"""

# Reset
dut.rst <= 1
dut.test_id <= 2
dut.rst.value = 1
dut.test_id.value = 2
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
setup_dut(dut)
await Timer(CLK_PERIOD_NS * 10, units='ns')
dut.rst <= 0
dut.rst.value = 0

ADDRESS = 0x00
DATA = 0xAB
Expand Down Expand Up @@ -127,12 +127,12 @@ async def write_fail(dut):
the user attempted to write to an invalid address.
"""
# Reset
dut.rst <= 1
dut.test_id <= 3
dut.rst.value = 1
dut.test_id.value = 3
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
setup_dut(dut)
await Timer(CLK_PERIOD_NS * 10, units='ns')
dut.rst <= 0
dut.rst.value = 0

ADDRESS = 0x08
DATA = 0xAB
Expand All @@ -158,12 +158,12 @@ async def read_fail(dut):
the user attempted to read from an invalid address.
"""
# Reset
dut.rst <= 1
dut.test_id <= 4
dut.rst.value = 1
dut.test_id.value = 4
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
setup_dut(dut)
await Timer(CLK_PERIOD_NS * 10, units='ns')
dut.rst <= 0
dut.rst.value = 0

ADDRESS = 0x08
DATA = 0xAB
Expand Down
8 changes: 5 additions & 3 deletions examples/dff/tests/dff_cocotb.py
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.triggers import ReadOnly, RisingEdge
from cocotb.binary import BinaryValue
from cocotb.regression import TestFactory

Expand Down Expand Up @@ -136,9 +136,9 @@ def stop(self):
async def run_test(dut):
"""Setup testbench and run a test."""

cocotb.fork(Clock(dut.c, 10, 'us').start(start_high=False))
cocotb.start_soon(Clock(dut.c, 10, 'us').start(start_high=False))

tb = DFF_TB(dut, init_val=BinaryValue(0))
tb = DFF_TB(dut, init_val=BinaryValue("0"))

clkedge = RisingEdge(dut.c)

Expand All @@ -149,6 +149,8 @@ async def run_test(dut):

# Stop generation of input data. One more clock cycle is needed to capture
# the resulting output of the DUT.

await ReadOnly()
tb.stop()
await clkedge

Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ async def reset(dut, duration=10):
async def initial_hal_test(dut, debug=True):
"""Example of using the software HAL against cosim testbench"""

cocotb.fork(Clock(dut.clk, 5, units='ns').start())
cocotb.start_soon(Clock(dut.clk, 5, units='ns').start())
await reset(dut)

# Create the avalon master and direct our HAL calls to that
Expand Down
16 changes: 8 additions & 8 deletions examples/endian_swapper/tests/test_endian_swapper.py
Original file line number Diff line number Diff line change
Expand Up @@ -158,7 +158,7 @@ def __init__(self, dut, debug=False):

self.csr = AvalonMaster(dut, "csr", dut.clk)

cocotb.fork(stream_out_config_setter(dut, self.stream_out,
cocotb.start_soon(stream_out_config_setter(dut, self.stream_out,
self.stream_in))

# Create a scoreboard on the stream_out bus
Expand Down Expand Up @@ -186,26 +186,26 @@ def model(self, transaction):

async def reset(self, duration=20):
self.dut._log.debug("Resetting DUT")
self.dut.reset_n <= 0
self.stream_in.bus.valid <= 0
self.dut.reset_n.value = 0
self.stream_in.bus.valid.value = 0
await Timer(duration, units='ns')
await RisingEdge(self.dut.clk)
self.dut.reset_n <= 1
self.dut.reset_n.value = 1
self.dut._log.debug("Out of reset")


async def run_test(dut, data_in=None, config_coroutine=None, idle_inserter=None,
backpressure_inserter=None):

cocotb.fork(Clock(dut.clk, 10, units='ns').start())
cocotb.start_soon(Clock(dut.clk, 10, units='ns').start())
tb = EndianSwapperTB(dut)

await tb.reset()
dut.stream_out_ready <= 1
dut.stream_out_ready.value = 1

# Start off any optional coroutines
if config_coroutine is not None:
cocotb.fork(config_coroutine(tb.csr))
cocotb.start_soon(config_coroutine(tb.csr))
if idle_inserter is not None:
tb.stream_in.set_valid_generator(idle_inserter())
if backpressure_inserter is not None:
Expand Down Expand Up @@ -260,7 +260,7 @@ async def wavedrom_test(dut):
"""
Generate a JSON wavedrom diagram of a trace and save it to wavedrom.json
"""
cocotb.fork(Clock(dut.clk, 10, units='ns').start())
cocotb.start_soon(Clock(dut.clk, 10, units='ns').start())
await RisingEdge(dut.clk)
tb = EndianSwapperTB(dut)
await tb.reset()
Expand Down
32 changes: 16 additions & 16 deletions examples/mean/tests/test_mean.py
Original file line number Diff line number Diff line change
Expand Up @@ -36,21 +36,21 @@ async def value_test(dut, nums):
dut._log.info('Detected DATA_WIDTH = %d, BUS_WIDTH = %d' %
(DATA_WIDTH, BUS_WIDTH))

cocotb.fork(Clock(dut.clk, CLK_PERIOD_NS, units='ns').start())
cocotb.start_soon(Clock(dut.clk, CLK_PERIOD_NS, units='ns').start())

dut.rst <= 1
dut.rst.value = 1
for i in range(BUS_WIDTH):
dut.i_data[i] <= 0
dut.i_valid <= 0
dut.i_data[i].value = 0
dut.i_valid.value = 0
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
dut.rst <= 0
dut.rst.value = 0

for i in range(BUS_WIDTH):
dut.i_data[i] <= nums[i]
dut.i_valid <= 1
dut.i_data[i].value = nums[i]
dut.i_valid.value = 1
await RisingEdge(dut.clk)
dut.i_valid <= 0
dut.i_valid.value = 0
await RisingEdge(dut.clk)
got = int(dut.o_data.value)

Expand Down Expand Up @@ -102,28 +102,28 @@ async def mean_randomised_test(dut):
dut._log.info('Detected DATA_WIDTH = %d, BUS_WIDTH = %d' %
(DATA_WIDTH, BUS_WIDTH))

cocotb.fork(Clock(dut.clk, CLK_PERIOD_NS, units='ns').start())
cocotb.start_soon(Clock(dut.clk, CLK_PERIOD_NS, units='ns').start())

dut.rst <= 1
dut.rst.value = 1
for i in range(BUS_WIDTH):
dut.i_data[i] <= 0
dut.i_valid <= 0
dut.i_data[i].value = 0
dut.i_valid.value = 0
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
dut.rst <= 0
dut.rst.value = 0

for j in range(10):
nums = []
for i in range(BUS_WIDTH):
x = random.randint(0, 2**DATA_WIDTH - 1)
dut.i_data[i] <= x
dut.i_data[i].value = x
nums.append(x)
dut.i_valid <= 1
dut.i_valid.value = 1

nums_mean = sum(nums) // BUS_WIDTH
exp_out.append(nums_mean)
await RisingEdge(dut.clk)
dut.i_valid <= 0
dut.i_valid.value = 0

await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
4 changes: 2 additions & 2 deletions src/cocotb_bus/drivers/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ def start(self, generator: Iterable[Tuple[int, int]] = None) -> None:

bit_driver.start((1, i % 5) for i in itertools.count())
"""
self._cr = cocotb.fork(self._cr_twiddler(generator=generator))
self._cr = cocotb.start_soon(self._cr_twiddler(generator=generator))

def stop(self):
"""Stop generating data."""
Expand Down Expand Up @@ -89,7 +89,7 @@ def __init__(self):
self.log = SimLog("cocotb.driver.%s" % (type(self).__qualname__))

# Create an independent coroutine which can send stuff
self._thread = cocotb.scheduler.add(self._send_thread())
self._thread = cocotb.start_soon(self._send_thread())

async def _acquire_lock(self):
if self.busy:
Expand Down
6 changes: 3 additions & 3 deletions src/cocotb_bus/drivers/amba.py
Original file line number Diff line number Diff line change
Expand Up @@ -301,7 +301,7 @@ async def write(
write_data = self._send_write_data(address, value, burst, size,
data_latency, byte_enable, sync)

await Combine(cocotb.fork(write_address), cocotb.fork(write_data))
await Combine(cocotb.start_soon(write_address), cocotb.start_soon(write_data))

async with self.write_response_busy:
# Wait for the response
Expand Down Expand Up @@ -597,8 +597,8 @@ def __init__(self, entity, name, clock, memory, callback=None, event=None,
self.read_address_busy = Lock("%s_rabusy" % name)
self.write_data_busy = Lock("%s_wbusy" % name)

cocotb.fork(self._read_data())
cocotb.fork(self._write_data())
cocotb.start_soon(self._read_data())
cocotb.start_soon(self._write_data())

def _size_to_bytes_in_beat(self, AxSIZE):
if AxSIZE < 7:
Expand Down
7 changes: 4 additions & 3 deletions src/cocotb_bus/drivers/avalon.py
Original file line number Diff line number Diff line change
Expand Up @@ -14,10 +14,11 @@
import random
from typing import Iterable, Union, Optional

from scapy.utils import hexdump

import cocotb
from cocotb.decorators import coroutine
from cocotb.triggers import RisingEdge, FallingEdge, ReadOnly, NextTimeStep
from cocotb.utils import hexdump
from cocotb.binary import BinaryValue
from cocotb.result import TestError

Expand Down Expand Up @@ -259,7 +260,7 @@ def __init__(self, entity, name, clock, readlatency_min=1,
self._readlatency_min = readlatency_min
self._readlatency_max = readlatency_max
self._responses = []
self._coro = cocotb.fork(self._respond())
self._coro = cocotb.start_soon(self._respond())

if hasattr(self.bus, "readdatavalid"):
self.bus.readdatavalid.setimmediatevalue(0)
Expand Down Expand Up @@ -790,7 +791,7 @@ async def _driver_send(self, pkt: Union[bytes, Iterable], sync: bool = True, cha
# Avoid spurious object creation by recycling
if isinstance(pkt, bytes):
self.log.debug("Sending packet of length %d bytes", len(pkt))
self.log.debug(hexdump(pkt))
self.log.debug(f"Sending Packet:\n{hexdump(pkt, dump=True)}")
await self._send_string(pkt, sync=sync, channel=channel)
self.log.debug("Successfully sent packet of length %d bytes", len(pkt))
elif isinstance(pkt, str):
Expand Down
5 changes: 3 additions & 2 deletions src/cocotb_bus/drivers/xgmii.py
Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,9 @@
import struct
import zlib

from scapy.utils import hexdump

from cocotb.triggers import RisingEdge
from cocotb.utils import hexdump
from cocotb.binary import BinaryValue
from cocotb.handle import SimHandleBase

Expand Down Expand Up @@ -162,7 +163,7 @@ async def _driver_send(self, pkt: bytes, sync: bool = True) -> None:
pkt = self.layer1(bytes(pkt))

self.log.debug("Sending packet of length %d bytes" % len(pkt))
self.log.debug(hexdump(pkt))
self.log.debug(f"Sending Packet:\n{hexdump(pkt, dump=True)}")

clkedge = RisingEdge(self.clock)
if sync:
Expand Down
2 changes: 1 addition & 1 deletion src/cocotb_bus/monitors/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ def __init__(self, callback=None, event=None):
self.add_callback(callback)

# Create an independent coroutine which can receive stuff
self._thread = cocotb.scheduler.add(self._monitor_recv())
self._thread = cocotb.start_soon(self._monitor_recv())

def kill(self):
"""Kill the monitor coroutine."""
Expand Down
5 changes: 3 additions & 2 deletions src/cocotb_bus/monitors/avalon.py
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,8 @@

import warnings

from cocotb.utils import hexdump
from scapy.utils import hexdump

from cocotb.triggers import RisingEdge
from cocotb.binary import BinaryValue

Expand Down Expand Up @@ -190,7 +191,7 @@ def valid():

if self.bus.endofpacket.value:
self.log.info("Received a packet of %d bytes", len(pkt))
self.log.debug(hexdump(pkt))
self.log.debug(f"Received Packet:\n{hexdump(pkt, dump=True)}")
self.channel = channel
if self.report_channel:
self._recv({"data": pkt, "channel": channel})
Expand Down
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