Basic Virtual Memory Implementation Fixes & Improvements #165

nemecad · 2025-09-04T10:53:57Z

This PR addresses some previous feedback, most notably:

Set-associative TLB (machine::TLB): Implements a set-associative Translation Lookaside Buffer (TLB) frontend over physical memory, handling virtual to physical translation, flush, and replacement policy.
Pluggable Replacement Policies (machine::TLBPolicy): Abstract TLB replacement policy interface & implementations (RAND, LRU, LFU, PLRU) for set-associative tables.
SV32 Page-Table Walker (machine::PageTableWalker): Performs multi-level page-table walks (SV32) in memory to resolve a virtual address to a physical one.
Sv32Pte Bitfield Helpers (sv32.h): SV32-specific definitions: page-table entry (PTE) bitfields, shifts/masks, and PTE to physical address helpers.
VirtualAddress (virtual_address.h): Lightweight VirtualAddress wrapper offering raw access, alignment checks, arithmetic, and comparisons.
Add supervisor CSRs and sstatus handling: supervisor CSRs (sstatus, stvec, sscratch, sepc, scause, stval, satp) and a write handler that presents sstatus as a masked view of mstatus so supervisor-visible bits stay in sync.
Store current privilege level in CoreState: tracking of the hart's current privilege level in CoreState so exception/return handling and visualization can read/update it from the central CoreState structure.

Tests:

Add SV32 page-table + TLB integration tests: a set of small assembly tests that exercise the SV32 page-table walker, SATP enablement and the new TLB code. The tests create a root page table and map a virtual page at 0xC4000000, then exercise several scenarios. The tests verify page-table walker behaviour, SATP switching and TLB caching/flush logic. Tests were written based on the consultation.

UI Components:

Show current privilege level in core state view:

Virtual memory configuration to NewDialog:

TLB visualization and statistics dock:

VM toggle and "As CPU" memory access view:

Add tracking of the hart's current privilege level to the core state so code handling exceptions/returns and visualization can read/update it from the central CoreState structure.

Add supervisor CSRs (sstatus, stvec, sscratch, sepc, scause, stval, satp) and a write handler that presents sstatus as a masked view of mstatus so supervisor-visible bits stay in sync.

Add a configurable TLB and a full SV32 page-table walker. The walker implements two-level SV32 walks and raises page-fault exceptions for invalid mappings. The TLB supports I/D caches, SATP awareness (SATP writes flush the TLB), and caching of resolved mappings.

Add a set of small assembly tests that exercise the SV32 page-table walker, SATP enablement and the new TLB code. The tests create a root page table and map a virtual page at 0xC4000000, then exercise several scenarios. The tests verify page-table walker behaviour, SATP switching and TLB caching/flush logic. Tests were written based on the consultation.

jdupak · 2025-09-28T17:18:57Z

src/gui/CMakeLists.txt

+        windows/tlb/tlbview.h
+        windows/tlb/tlbview.cpp
+        windows/tlb/tlbdock.cpp
+        windows/tlb/tlbdock.h)


This does no seem right - source files in icon path.

jdupak · 2025-09-28T17:24:54Z

src/gui/dialogs/new/newdialog.cpp

+void NewDialog::vm_enabled_change(bool v) {
+    if (config->get_vm_enabled() != v) {
+        config->set_vm_enabled(v);
+        switch2custom();


Nit: please prefer a consistent naming convention switch_to_custom. Also try to think of a more descriptive name or add a comment.

jdupak · 2025-09-28T17:31:08Z

src/gui/windows/tlb/tlbview.cpp

+}
+
+TLBViewScene::~TLBViewScene() {
+    delete[] block;


Can we make this RAII?

jdupak · 2025-09-28T17:44:57Z

src/gui/windows/tlb/tlbview.h

+    unsigned way_index;
+    unsigned rows;
+    QGraphicsSimpleTextItem **validity;
+    QGraphicsSimpleTextItem **asid;


@nemecad This is an important comment with a more generic theme:
Please avoid using pointer type for arrays at all cost. That is extremely confusing and dangerous. Just use std::vector or std::array. As a rule of thumb, new keyword should be avoided unless it is required by Qt (method that take ownership of the pointer). Such pointers should be marked by the QT_OWNED macro to make it clear.
For owned types that need to be allocated (because of Qt requirements), use Box<T>.

For any class members, please:

prefer value types, if not possible use Box (shorthand for QtScopedPointer), std::vector or std::array.

Prefer references over pointers, of not possible mark them with macro BORROWED (another custom class) or QT_OWNED. And consider adding a comment explaining the lifetime if it is not obvious.

jdupak · 2025-09-28T17:52:31Z

src/machine/CMakeLists.txt

 		memory/cache/cache_policy.cpp
 		memory/frontend_memory.cpp
 		memory/memory_bus.cpp
+                memory/tlb/tlb.cpp


jdupak · 2025-09-28T17:59:57Z

src/machine/machine.cpp

+}
+
+const TLB *Machine::get_tlb_program() const {
+    return tlb_program ? &*tlb_program : nullptr;


There is a method for this (get iirc). I am not sure if this is correct.

jdupak · 2025-09-28T18:00:16Z

src/machine/machine.h

 #include <QObject>
 #include <QTimer>
 #include <cstdint>
+#include <iostream>


Why is this needed?

jdupak · 2025-09-28T18:00:52Z

src/machine/machineconfig.cpp


 #include <QMap>
 #include <utility>
+#include <iostream>


Why is this needed?

jdupak · 2025-09-28T18:02:32Z

src/machine/memory/frontend_memory.cpp

    // See example in read_generic for byteswap explanation.
    const T swapped_value
        = byteswap_if(value, this->simulated_machine_endian != NATIVE_ENDIAN);
+    if (auto tlb = dynamic_cast<TLB *>(this)) {


This makes me worried. This object model does not make much sense. See my comments on the previous PR.

jdupak · 2025-09-28T18:04:33Z

src/machine/memory/virtual/sv32.h

+    static constexpr uint64_t PHYS_PPN_START = 0x200; // I have noticed that programs are loaded into memory starting at 0x200.
+
+    // Sv32Pte wraps the raw 32-bit PTE value and provides helpers to read flags and fields.
+    // Layout (bit indices):


jdupak · 2025-09-28T18:14:08Z

I am getting this weird zoom.

jdupak · 2025-09-28T18:14:47Z

Notice that address sanitizer is failing in CI.

jdupak · 2025-09-28T18:15:58Z

src/gui/windows/tlb/tlbview.h

+        void tlb_update(unsigned way, unsigned set, bool valid, unsigned asid, quint64 vpn, quint64 phys, bool write);
+
+private:
+    const machine::TLB *tlb;


Who owns this pointer?

jdupak · 2025-09-28T18:17:38Z

src/machine/memory/tlb/tlb.h

+#include <cstdint>
+
+namespace machine {
+enum TLBType { PROGRAM, DATA };


Why does LTB need to know this?

ppisa · 2025-09-29T08:51:35Z

@jdupak thanks for review of interfacing to the memory model architecture.

ppisa · 2025-09-29T08:51:45Z

From my side, the changes to the processor pipeline diagram has been applied directly to the SVG files (src/gui/windows/coreview/schemas), but current design uses DRAW.IO source (extras/core_graphics) as the authoritative source of the pipeline visualization and SVGs are generated from this file. So the commit with SVG change should include extras/core_graphics/diagram.drawio change as well or extras/core_graphics/diagram.drawio change should be commit before SVG files regeneration commit. In long term, I would lean to single SVG file with tags for conditional rendering, but we have not got to that state yet and current solution implemented by @jdupak is based on DRAW.IO and exports controlled by tagging (some documentation there docs/developer/coreview-graphics/using-drawio-diagram.md).

ppisa · 2025-09-29T08:55:46Z

For memory view, I would not complicate it with Show virtual checkbox. I would use only switching between As CPU (VMA), Cached and Raw.

Add privilege level mapping to the GUI so the current hart privilege (UNPRIV, SUPERV, HYPERV, MACHINE) is displayed in core state visualization.

Extend NewDialog with controls for virtual memory setup, including TLB number of sets, associativity, and replacement policy.

Introduce new components for displaying and tracking TLB state similar to cache. TLBViewBlock and TLBAddressBlock render per-set and per-way TLB contents, updated on tlb_update signals. TLBViewScene assembles these views based on associativity. TLBDock integrates into the GUI, showing hit/miss counts, memory accesses, stall cycles, hit rate, and speed improvement, with live updates from the TLB.

Introduce an "As CPU (VMA)" access option in the cached access selector to render memory contents as observed by the CPU through the frontend interface.

This resolves the incorrect zoom behavior.

Store only `current_privilege_u` in CoreState and use accessor methods to convert to CSR::PrivilegeLevel. Resolves previous issues with duplicated privilege representation.

Removes the previous approach; instead, TLBs are now created every time. If virtual memory is disabled, the TLB logic is skipped.

Include new supervisor registers in the expected output to fix CI failures.

nemecad · 2025-10-05T19:38:26Z

@ppisa @jdupak Thank you for your detailed feedback. I appreciate it and have made some changes based on your review. I would be grateful for any further feedback.

nemecad added 4 commits September 3, 2025 16:58

Machine: store current privilege level in CoreState

7bc6c89

Add tracking of the hart's current privilege level to the core state so code handling exceptions/returns and visualization can read/update it from the central CoreState structure.

Machine: add supervisor CSRs and sstatus handling

3ca6851

Add supervisor CSRs (sstatus, stvec, sscratch, sepc, scause, stval, satp) and a write handler that presents sstatus as a masked view of mstatus so supervisor-visible bits stay in sync.

jdupak self-requested a review September 28, 2025 17:17

jdupak reviewed Sep 28, 2025

View reviewed changes

GUI: show current privilege level in core state view

3b888b1

Add privilege level mapping to the GUI so the current hart privilege (UNPRIV, SUPERV, HYPERV, MACHINE) is displayed in core state visualization.

nemecad force-pushed the feature/sv32-vm-tlb-ptw-cleanup branch 4 times, most recently from aa7df79 to 7b06705 Compare October 5, 2025 18:34

nemecad added 7 commits October 5, 2025 21:16

GUI: add virtual memory configuration to NewDialog

fe46efc

Extend NewDialog with controls for virtual memory setup, including TLB number of sets, associativity, and replacement policy.

GUI: add "As CPU (VMA)" memory access view

e89eb87

Introduce an "As CPU (VMA)" access option in the cached access selector to render memory contents as observed by the CPU through the frontend interface.

GUI: fix zoom scaling issue

59110d9

This resolves the incorrect zoom behavior.

Machine: eliminate data duplication for privilege state

a63b8c1

Store only `current_privilege_u` in CoreState and use accessor methods to convert to CSR::PrivilegeLevel. Resolves previous issues with duplicated privilege representation.

Machine: refactor TLB setup

48f2cfb

Removes the previous approach; instead, TLBs are now created every time. If virtual memory is disabled, the TLB logic is skipped.

Tests: update stalls test expected output

ca4300b

Include new supervisor registers in the expected output to fix CI failures.

nemecad force-pushed the feature/sv32-vm-tlb-ptw-cleanup branch from 0bb04d1 to ca4300b Compare October 5, 2025 19:16

Basic Virtual Memory Implementation Fixes & Improvements #165

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nemecad commented Sep 4, 2025

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jdupak commented Sep 28, 2025

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jdupak commented Sep 28, 2025

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ppisa commented Sep 29, 2025

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ppisa commented Sep 29, 2025

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ppisa commented Sep 29, 2025

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nemecad commented Oct 5, 2025

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