SPI: Implement missing traits

esp-hal/CHANGELOG.md

@@ -34,6 +34,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - `{DmaRxBuf, DmaTxBuf, DmaRxTxBuf}::set_burst_config` (#2543)
 - ESP32-S2: DMA support for AES (#2699)
 - Added `transfer_in_place_async` and embedded-hal-async implementation to `Spi` (#2691)
+- `spi::master::Config` now implements `Hash` (#2823)
+- `spi::master` drivers now implement `PartialEq` and `Eq` (#2823)
 
 ### Changed
 

esp-hal/src/dma/buffers.rs

@@ -469,7 +469,7 @@ pub struct BufView<T>(T);
 /// This is a contiguous buffer linked together by DMA descriptors of length
 /// 4095 at most. It can only be used for transmitting data to a peripheral's
 /// FIFO. See [DmaRxBuf] for receiving data.
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct DmaTxBuf {
     descriptors: DescriptorSet<'static>,
@@ -650,6 +650,8 @@ unsafe impl DmaTxBuffer for DmaTxBuf {
 /// This is a contiguous buffer linked together by DMA descriptors of length
 /// 4092. It can only be used for receiving data from a peripheral's FIFO.
 /// See [DmaTxBuf] for transmitting data.
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct DmaRxBuf {
     descriptors: DescriptorSet<'static>,
     buffer: &'static mut [u8],

esp-hal/src/dma/gdma.rs

@@ -25,6 +25,8 @@ use crate::{
 };
 
 /// An arbitrary GDMA channel
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct AnyGdmaChannel(u8);
 
 impl Peripheral for AnyGdmaChannel {
@@ -51,6 +53,8 @@ impl DmaChannel for AnyGdmaChannel {
 }
 
 /// An arbitrary GDMA RX channel
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct AnyGdmaRxChannel(u8);
 
 impl Peripheral for AnyGdmaRxChannel {
@@ -68,6 +72,8 @@ impl DmaChannelConvert<AnyGdmaRxChannel> for AnyGdmaRxChannel {
 }
 
 /// An arbitrary GDMA TX channel
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct AnyGdmaTxChannel(u8);
 
 impl Peripheral for AnyGdmaTxChannel {

esp-hal/src/dma/mod.rs

@@ -215,7 +215,7 @@ where
 
 bitfield::bitfield! {
     /// DMA descriptor flags.
-    #[derive(Clone, Copy)]
+    #[derive(Clone, Copy, PartialEq, Eq)]
     pub struct DmaDescriptorFlags(u32);
 
     u16;
@@ -272,7 +272,7 @@ impl defmt::Format for DmaDescriptorFlags {
 }
 
 /// A DMA transfer descriptor.
-#[derive(Clone, Copy, Debug)]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct DmaDescriptor {
     /// Descriptor flags.
@@ -1071,7 +1071,7 @@ pub const fn descriptor_count(buffer_size: usize, chunk_size: usize, is_circular
     buffer_size.div_ceil(chunk_size)
 }
 
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 struct DescriptorSet<'a> {
     descriptors: &'a mut [DmaDescriptor],
@@ -1588,18 +1588,18 @@ pub type PeripheralTxChannel<T> = <PeripheralDmaChannel<T> as DmaChannel>::Tx;
 
 #[doc(hidden)]
 pub trait DmaRxChannel:
-    RxRegisterAccess + InterruptAccess<DmaRxInterrupt> + Peripheral<P = Self>
+    RxRegisterAccess + InterruptAccess<DmaRxInterrupt> + Peripheral<P = Self> + Debug + PartialEq + Eq
 {
 }
 
 #[doc(hidden)]
 pub trait DmaTxChannel:
-    TxRegisterAccess + InterruptAccess<DmaTxInterrupt> + Peripheral<P = Self>
+    TxRegisterAccess + InterruptAccess<DmaTxInterrupt> + Peripheral<P = Self> + Debug + PartialEq + Eq
 {
 }
 
 /// A description of a DMA Channel.
-pub trait DmaChannel: Peripheral<P = Self> {
+pub trait DmaChannel: Peripheral<P = Self> + Debug + PartialEq + Eq {
     /// A description of the RX half of a DMA Channel.
     type Rx: DmaRxChannel;
 
@@ -1808,6 +1808,8 @@ fn create_guard(_ch: &impl RegisterAccess) -> PeripheralGuard {
 // DMA receive channel
 #[non_exhaustive]
 #[doc(hidden)]
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct ChannelRx<'a, Dm, CH>
 where
     Dm: Mode,
@@ -2108,6 +2110,8 @@ pub trait Tx: crate::private::Sealed {
 
 /// DMA transmit channel
 #[doc(hidden)]
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct ChannelTx<'a, Dm, CH>
 where
     Dm: Mode,
@@ -2448,6 +2452,8 @@ pub trait InterruptAccess<T: EnumSetType>: crate::private::Sealed {
 
 /// DMA Channel
 #[non_exhaustive]
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Channel<'d, Dm, CH>
 where
     Dm: Mode,

esp-hal/src/dma/pdma/crypto.rs

@@ -11,6 +11,8 @@ use crate::{
 pub(super) type CryptoRegisterBlock = crate::peripherals::crypto_dma::RegisterBlock;
 
 /// The RX half of a Crypto DMA channel.
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct CryptoDmaRxChannel(pub(crate) CryptoDmaChannel);
 
 impl crate::private::Sealed for CryptoDmaRxChannel {}
@@ -24,6 +26,8 @@ impl Peripheral for CryptoDmaRxChannel {
 }
 
 /// The TX half of a Crypto DMA channel.
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct CryptoDmaTxChannel(pub(crate) CryptoDmaChannel);
 
 impl crate::private::Sealed for CryptoDmaTxChannel {}
@@ -437,6 +441,8 @@ impl InterruptAccess<DmaRxInterrupt> for CryptoDmaRxChannel {
 
 #[doc = "DMA channel suitable for CRYPTO"]
 #[non_exhaustive]
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct CryptoDmaChannel {}
 
 impl crate::private::Sealed for CryptoDmaChannel {}

esp-hal/src/dma/pdma/i2s.rs

@@ -5,6 +5,8 @@ use crate::{asynch::AtomicWaker, dma::*, peripheral::Peripheral, peripherals::In
 pub(super) type I2sRegisterBlock = crate::peripherals::i2s0::RegisterBlock;
 
 /// The RX half of an arbitrary I2S DMA channel.
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct AnyI2sDmaRxChannel(pub(crate) AnyI2sDmaChannel);
 
 impl crate::private::Sealed for AnyI2sDmaRxChannel {}
@@ -18,6 +20,8 @@ impl Peripheral for AnyI2sDmaRxChannel {
 }
 
 /// The TX half of an arbitrary I2S DMA channel.
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct AnyI2sDmaTxChannel(pub(crate) AnyI2sDmaChannel);
 
 impl crate::private::Sealed for AnyI2sDmaTxChannel {}

esp-hal/src/dma/pdma/spi.rs

@@ -5,6 +5,8 @@ use crate::{asynch::AtomicWaker, dma::*, peripheral::Peripheral, peripherals::In
 pub(super) type SpiRegisterBlock = crate::peripherals::spi2::RegisterBlock;
 
 /// The RX half of an arbitrary SPI DMA channel.
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct AnySpiDmaRxChannel(pub(crate) AnySpiDmaChannel);
 
 impl crate::private::Sealed for AnySpiDmaRxChannel {}
@@ -18,6 +20,8 @@ impl Peripheral for AnySpiDmaRxChannel {
 }
 
 /// The TX half of an arbitrary SPI DMA channel.
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct AnySpiDmaTxChannel(pub(crate) AnySpiDmaChannel);
 
 impl crate::private::Sealed for AnySpiDmaTxChannel {}

esp-hal/src/macros.rs

@@ -90,7 +90,7 @@ macro_rules! any_peripheral {
     }) => {
         paste::paste! {
             $(#[$meta])*
-            #[derive(Debug, PartialEq)]
+            #[derive(Debug, PartialEq, Eq)]
             #[cfg_attr(feature = "defmt", derive(defmt::Format))]
             $vis struct $name([< $name Inner >]);
             impl $crate::private::Sealed for $name {}
@@ -109,7 +109,7 @@ macro_rules! any_peripheral {
             }
 
             $(#[$meta])*
-            #[derive(Debug, PartialEq)]
+            #[derive(Debug, PartialEq, Eq)]
             enum [< $name Inner >] {
                 $(
                     $(#[cfg($variant_meta)])*

esp-hal/src/spi/master.rs

@@ -440,6 +440,15 @@ pub struct Config {
     pub write_bit_order: SpiBitOrder,
 }
 
+impl core::hash::Hash for Config {
+    fn hash<H: core::hash::Hasher>(&self, state: &mut H) {
+        self.frequency.to_Hz().hash(state); // HertzU32 doesn't implement Hash
+        self.mode.hash(state);
+        self.read_bit_order.hash(state);
+        self.write_bit_order.hash(state);
+    }
+}
+
 impl Default for Config {
     fn default() -> Self {
         use fugit::RateExtU32;
@@ -459,7 +468,7 @@ impl Default for Config {
 pub enum ConfigError {}
 
 /// SPI peripheral driver
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Spi<'d, Dm, T = AnySpi> {
     spi: PeripheralRef<'d, T>,
@@ -884,6 +893,8 @@ mod dma {
     /// [`SpiDmaBus`] via `with_buffers` to get access
     /// to a DMA capable SPI bus that implements the
     /// embedded-hal traits.
+    #[derive(PartialEq, Eq)]
+    #[cfg_attr(feature = "defmt", derive(defmt::Format))]
     pub struct SpiDma<'d, Dm, T = AnySpi>
     where
         T: Instance,
@@ -951,7 +962,7 @@ mod dma {
         /// This method returns a debug struct with the name "SpiDma" without
         /// exposing internal details.
         fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-            f.debug_struct("SpiDma").finish()
+            f.debug_struct("SpiDma").field("spi", &self.spi).finish()
         }
     }
 
@@ -1575,6 +1586,8 @@ mod dma {
     ///
     /// This structure is responsible for managing SPI transfers using DMA
     /// buffers.
+    #[derive(Debug, PartialEq, Eq)]
+    #[cfg_attr(feature = "defmt", derive(defmt::Format))]
     pub struct SpiDmaBus<'d, Dm, T = AnySpi>
     where
         T: Instance,
@@ -2290,7 +2303,9 @@ mod ehal1 {
 }
 
 /// SPI peripheral instance.
-pub trait PeripheralInstance: private::Sealed + Into<AnySpi> + DmaEligible + 'static {
+pub trait PeripheralInstance:
+    private::Sealed + Into<AnySpi> + DmaEligible + 'static + core::fmt::Debug
+{
     /// Returns the peripheral data describing this SPI instance.
     fn info(&self) -> &'static Info;
 }

esp-hal/src/system.rs

@@ -191,7 +191,8 @@ impl Drop for PeripheralGuard {
     }
 }
 
-#[derive(Debug)]
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub(crate) struct GenericPeripheralGuard<const P: u8> {}
 
 impl<const P: u8> GenericPeripheralGuard<P> {

esp-hal/src/timer/systimer.rs

@@ -265,7 +265,7 @@ impl Unit {
 }
 
 /// An alarm unit
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Alarm {
     comp: u8,

esp-hal/src/timer/timg.rs

@@ -366,7 +366,7 @@ impl Peripheral for Timer {
 }
 
 /// A timer within a Timer Group.
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Timer {
     register_block: *const RegisterBlock,