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GPIO interconnect #2128

Merged
merged 21 commits into from
Sep 11, 2024
Merged

GPIO interconnect #2128

merged 21 commits into from
Sep 11, 2024

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bugadani
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@bugadani bugadani commented Sep 9, 2024

Thank you for your contribution!

We appreciate the time and effort you've put into this pull request.
To help us review it efficiently, please ensure you've gone through the following checklist:

Submission Checklist 📝

  • I have updated existing examples or added new ones (if applicable).
  • I have used cargo xtask fmt-packages command to ensure that all changed code is formatted correctly.
  • My changes were added to the CHANGELOG.md in the proper section.
  • I have added necessary changes to user code to the Migration Guide.
  • My changes are in accordance to the esp-rs API guidelines

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Pull Request Details 📖

Description

This PR introduces the concept of a peripheral signal. Peripheral signals can be obtained from GPIO pins/pin drivers, the DummyPin (which... yeah, may go away probably), and Levels. These signals can then be passed to peripherals in place of the previous pin parameters (pins being a subset of signals, this is bw compatible).

The PR deletes AnyPin and replaces its functionality with InputSignal and OutputSignal. This also allowed me to rename ErasedPin to AnyPin.

Closes #1662

Testing

Changed HIL tests to use interconnects instead of external jumpers.

@bugadani bugadani force-pushed the interconnect branch 5 times, most recently from 7b8cd26 to e5e1e5b Compare September 9, 2024 21:43
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@Dominaezzz Dominaezzz left a comment

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I cannot thank you enough for taking care of this!! I've been wanting this feature for so long and never had the time to implement it.

I hope my notes in the linked issue were somewhat useful.

esp-hal/src/pcnt/channel.rs Show resolved Hide resolved
esp-hal/src/spi/master.rs Show resolved Hide resolved
esp-hal/CHANGELOG.md Outdated Show resolved Hide resolved
esp-hal/src/gpio/mod.rs Outdated Show resolved Hide resolved
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Part of the test failures is, I believe, PCNT overwriting output pin configurations. It configures its source using init_input which immediately nukes the pin's output(!) function selection. How polite of it to do so, hopefully resolving won't require extensive shotgun surgery.

@bugadani bugadani force-pushed the interconnect branch 3 times, most recently from 722e132 to 86953ef Compare September 10, 2024 09:53
@bugadani bugadani mentioned this pull request Sep 10, 2024
@bugadani bugadani force-pushed the interconnect branch 5 times, most recently from dca5cc5 to 40531f9 Compare September 10, 2024 16:29
@bugadani bugadani marked this pull request as ready for review September 10, 2024 16:44
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NGL CI here is bizarre, rebasing on top of the S2 fix PR made C2 and C6 pass. Nonsense, but I'll take it.

@bugadani bugadani force-pushed the interconnect branch 2 times, most recently from 9ebae86 to f9eff0b Compare September 10, 2024 19:51
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@bjoernQ bjoernQ left a comment

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Thanks!

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@jessebraham jessebraham left a comment

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Thanks for this! Lots here but overall I think it looks quite good. I have some nitpicky comments that I will keep to myself but nothing else to add otherwise really, so LGTM.

@jessebraham jessebraham added this pull request to the merge queue Sep 11, 2024
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Please do tell your nitpicky comments, we can clear those up!

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@MabezDev MabezDev left a comment

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I really like how this turned out. I'm also glad ErasedPin is now AnyPin. I think we should do the same rename for ErasedTimer, but I'll file an issue for that.

LGTM!

@MabezDev MabezDev mentioned this pull request Sep 11, 2024
Merged via the queue into esp-rs:main with commit 7a733a7 Sep 11, 2024
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@bugadani bugadani deleted the interconnect branch September 11, 2024 15:31
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bjoernQ commented Sep 11, 2024

Seems I can finally close bjoernQ#1 since we have it now 🚀

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Expose GPIO matrix to users
5 participants