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GPIO interconnect #2128
GPIO interconnect #2128
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I cannot thank you enough for taking care of this!! I've been wanting this feature for so long and never had the time to implement it.
I hope my notes in the linked issue were somewhat useful.
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Part of the test failures is, I believe, PCNT overwriting output pin configurations. It configures its source using |
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NGL CI here is bizarre, rebasing on top of the S2 fix PR made C2 and C6 pass. Nonsense, but I'll take it. |
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Thanks!
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Thanks for this! Lots here but overall I think it looks quite good. I have some nitpicky comments that I will keep to myself but nothing else to add otherwise really, so LGTM.
Please do tell your nitpicky comments, we can clear those up! |
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I really like how this turned out. I'm also glad ErasedPin
is now AnyPin
. I think we should do the same rename for ErasedTimer
, but I'll file an issue for that.
LGTM!
Seems I can finally close bjoernQ#1 since we have it now 🚀 |
Thank you for your contribution!
We appreciate the time and effort you've put into this pull request.
To help us review it efficiently, please ensure you've gone through the following checklist:
Submission Checklist 📝
cargo xtask fmt-packages
command to ensure that all changed code is formatted correctly.CHANGELOG.md
in the proper section.Extra:
Pull Request Details 📖
Description
This PR introduces the concept of a peripheral signal. Peripheral signals can be obtained from GPIO pins/pin drivers, the DummyPin (which... yeah, may go away probably), and
Level
s. These signals can then be passed to peripherals in place of the previous pin parameters (pins being a subset of signals, this is bw compatible).The PR deletes AnyPin and replaces its functionality with InputSignal and OutputSignal. This also allowed me to rename ErasedPin to AnyPin.
Closes #1662
Testing
Changed HIL tests to use interconnects instead of external jumpers.