Consistent SPI Timing (Need review) #943
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esp-hal-common/src/spi/master.rs
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| @@ -2708,23 +2708,25 @@ pub trait Instance { | |||
| // FIXME: Using something like `core::slice::from_raw_parts` and | |||
| // `copy_from_slice` on the receive registers works only for the esp32 and | |||
| // esp32c3 varaints. The reason for this is unknown. | |||
| #[inline] | |||
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So I guess the comment above this attribute is no longer right?
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I think so, since the S3 and ESP32 should have the same processor?
| @@ -2628,6 +2629,7 @@ pub trait Instance { | |||
| /// you must ensure that the whole messages was written correctly, use | |||
| /// [`Self::flush`]. | |||
| // FIXME: See below. | |||
| #[ram] | |||
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I want to state here, too, that I think singling out SPI here isn't very elegant. Ideally all code should be as fast as possible, these getting the #[ram] treatment seems very arbitrary (to some who doesn't know the context). IMO before we start moving stuff into instruction ram somewhat haphazardly, we should probably come up with a systematic approach to tackle the problem.
That being said, good find!
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Related: #946 |
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@ProfFan thanks for this, sorry that it's just been sitting here for so long. Did you intend to rebase this and wrap up the work at any point, or can we go ahead and close this PR? |
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I think the key perf improvments were already merged? @ProfFan correct me if I'm wrong. |
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Yes！ |
Thank you!
With this I am getting consistent 9ns for 20 bytes at 36MHz with LTO on.
Write-only is ~8ns, so at least not too much penalty.
Thank you for your contribution.
Please make sure that your submission includes the following:
Must
errorsorwarnings.cargo fmtwas run.CHANGELOG.mdin the proper section.Nice to have