Add vpackev/vpackod

README.md

@@ -30,10 +30,6 @@ TODO List:
 
 ### vssrarn.bu.h/hu.w/wu.d
 
-### vpackev.b/h/w/d
-
-### vpackod.b/h/w/d
-
 ### vpickev.b/h/w/d
 
 ### vpickod.b/h/w/d

code/gen_impl.py

@@ -407,6 +407,20 @@
         )
         print(f"  }}", file=f)
         print(f"}}", file=f)
+    with open(f"vpackev_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(
+            f"  dst.{m}[i] = (i % 2 == 1) ? a.{m}[i-1] : b.{m}[i];",
+            file=f,
+        )
+        print(f"}}", file=f)
+    with open(f"vpackod_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(
+            f"  dst.{m}[i] = (i % 2 == 1) ? a.{m}[i] : b.{m}[i+1];",
+            file=f,
+        )
+        print(f"}}", file=f)
 
 for width in ["s", "d"]:
     m = members_fp[width]

code/gen_tb.py

@@ -74,6 +74,8 @@
     "vmul": (widths_signed, "v128 a, v128 b"),
     "vmulwev": (widths_vaddw, "v128 a, v128 b"),
     "vmulwod": (widths_vaddw, "v128 a, v128 b"),
+    "vpackev": (widths_signed, "v128 a, v128 b"),
+    "vpackod": (widths_signed, "v128 a, v128 b"),
     "vpcnt": (widths_signed, "v128 a"),
     "vrotr": (widths_signed, "v128 a, v128 b"),
     "vsadd": (widths_all, "v128 a, v128 b"),

code/vpackev_b.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vpackev_b(v128 a, v128 b) {
+  v128 dst;
+#include "vpackev_b.h"
+  return dst;
+}
+
+void test() { FUZZ2(vpackev_b); }

code/vpackev_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = (i % 2 == 1) ? a.byte[i - 1] : b.byte[i];
+}

code/vpackev_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vpackev_d(v128 a, v128 b) {
+  v128 dst;
+#include "vpackev_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vpackev_d); }

code/vpackev_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = (i % 2 == 1) ? a.dword[i - 1] : b.dword[i];
+}

code/vpackev_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vpackev_h(v128 a, v128 b) {
+  v128 dst;
+#include "vpackev_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vpackev_h); }

code/vpackev_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = (i % 2 == 1) ? a.half[i - 1] : b.half[i];
+}

code/vpackev_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vpackev_w(v128 a, v128 b) {
+  v128 dst;
+#include "vpackev_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vpackev_w); }

code/vpackev_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = (i % 2 == 1) ? a.word[i - 1] : b.word[i];
+}

code/vpackod_b.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vpackod_b(v128 a, v128 b) {
+  v128 dst;
+#include "vpackod_b.h"
+  return dst;
+}
+
+void test() { FUZZ2(vpackod_b); }

code/vpackod_b.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = (i % 2 == 1) ? a.byte[i] : b.byte[i + 1];
+}

code/vpackod_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vpackod_d(v128 a, v128 b) {
+  v128 dst;
+#include "vpackod_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vpackod_d); }

code/vpackod_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = (i % 2 == 1) ? a.dword[i] : b.dword[i + 1];
+}

code/vpackod_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vpackod_h(v128 a, v128 b) {
+  v128 dst;
+#include "vpackod_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vpackod_h); }

code/vpackod_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = (i % 2 == 1) ? a.half[i] : b.half[i + 1];
+}

code/vpackod_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vpackod_w(v128 a, v128 b) {
+  v128 dst;
+#include "vpackod_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vpackod_w); }

code/vpackod_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = (i % 2 == 1) ? a.word[i] : b.word[i + 1];
+}

docs/lsx/misc.md

@@ -1,6 +1,26 @@
 # Misc
 
+{{ vilvh('b') }}
+{{ vilvh('h') }}
+{{ vilvh('w') }}
+{{ vilvh('d') }}
+
+{{ vilvl('b') }}
+{{ vilvl('h') }}
+{{ vilvl('w') }}
+{{ vilvl('d') }}
+
 {{ vinsgr2vr('b') }}
 {{ vinsgr2vr('h') }}
 {{ vinsgr2vr('w') }}
-{{ vinsgr2vr('d') }}
+{{ vinsgr2vr('d') }}
+
+{{ vpackev('b') }}
+{{ vpackev('h') }}
+{{ vpackev('w') }}
+{{ vpackev('d') }}
+
+{{ vpackod('b') }}
+{{ vpackod('h') }}
+{{ vpackod('w') }}
+{{ vpackod('d') }}

main.py

@@ -697,4 +697,22 @@ def vsrar(name):
             intrinsic=f"__m128i __lsx_vsrar_{name} (__m128i a, __m128i b)",
             instr=f"vsrar.{name} vr, vr, vr",
             desc=f"Arithmetic right shift (with rounding) the signed {width}-bit elements in `a` by elements in `b`, store the result to `dst`.",
+        )
+
+    @env.macro
+    def vpackev(name):
+        width = widths[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vpackev_{name} (__m128i a, __m128i b)",
+            instr=f"vpackev.{name} vr, vr, vr",
+            desc=f"Collect and pack even-positioned {width}-bit elements in `a` and `b` and store `dst`.",
+        )
+
+    @env.macro
+    def vpackod(name):
+        width = widths[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vpackod_{name} (__m128i a, __m128i b)",
+            instr=f"vpackod.{name} vr, vr, vr",
+            desc=f"Collect and pack odd-positioned {width}-bit elements in `a` and `b` and store `dst`.",
         )