Add vextl

README.md

@@ -344,12 +344,8 @@ Vector Multiplication High
 
 ### vsllwil.h.b/w.h/d.w
 
-### vextl.q.d
-
 ### vsllwil.hu.bu/wu.hu/du.wu
 
-### vextl.qu.du
-
 ### vsat.b/h/w/d/bu/hu/wu/du
 
 ### vslli.b/h/w/d

code/gen_impl.py

@@ -87,6 +87,15 @@
         )
         print(f"}}", file=f)
 
+    if width == "d" or width == "du":
+        with open(f"vextl_{double_width}_{width}.h", "w") as f:
+            print(f"for (int i = 0;i < {128 // double_w};i++) {{", file=f)
+            print(
+                f"  dst.{double_m}[i] = ({sign}{double_w})({sign}{w})a.{m}[i];",
+                file=f,
+            )
+            print(f"}}", file=f)
+
 for width in ["b", "bu", "h", "hu", "w", "wu", "d", "du"]:
     double_width = double_widths[width]
     w = widths[width]

code/gen_tb.py

@@ -43,6 +43,7 @@
     "vclz": (widths_signed, "v128 a"),
     "vdiv": (widths_all, "v128 a, v128 b"),
     "vexth": (widths_vexth, "v128 a"),
+    "vextl": (["q_d", "qu_du"], "v128 a"),
 }
 
 for name in tb:

code/vextl_q_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vextl_q_d(v128 a) {
+  v128 dst;
+#include "vextl_q_d.h"
+  return dst;
+}
+
+void test() { FUZZ1(vextl_q_d); }

code/vextl_q_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 1; i++) {
+  dst.qword[i] = (s128)(s64)a.dword[i];
+}

code/vextl_qu_du.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vextl_qu_du(v128 a) {
+  v128 dst;
+#include "vextl_qu_du.h"
+  return dst;
+}
+
+void test() { FUZZ1(vextl_qu_du); }

code/vextl_qu_du.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 1; i++) {
+  dst.qword[i] = (u128)(u64)a.dword[i];
+}

docs/lsx/bitwise.md

@@ -90,3 +90,6 @@ Compute bitwise selection: for each bit position, if the bit in `a` equals to on
 {{ vexth('du', 'wu') }}
 {{ vexth('q', 'd') }}
 {{ vexth('qu', 'du') }}
+
+{{ vextl('q', 'd') }}
+{{ vextl('qu', 'du') }}

main.py

@@ -253,6 +253,17 @@ def vexth(name, name2):
             desc=f"Extend {signedness} {width2}-bit elements in the higher half of `a` to {width}-bit.",
         )
 
+    @env.macro
+    def vextl(name, name2):
+        width = widths[name[0]]
+        width2 = widths[name2[0]]
+        signedness = signednesses[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vextl_{name}_{name2} (__m128i a)",
+            instr=f"vextl.{name}.{name2} vr, vr",
+            desc=f"Extend {signedness} {width2}-bit elements in the lower half of `a` to {width}-bit.",
+        )
+
     @env.macro
     def vshuf_hwd(name):
         width = widths[name]