Fix intrinsics mismatch: vaddwod

jiegec · Dec 13, 2023 · c0915b2 · c0915b2
1 parent 329950b
commit c0915b2
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Showing 2 changed files with 8 additions and 4 deletions.
diff --git a/check_lsx.py b/check_lsx.py
@@ -1,10 +1,10 @@
 import os
 import glob
 
-# Update gh-pages before running:
-# git fetch origin
+# Initial worktree:
 # git worktree add -f ../gh-pages gh-pages
-# git -C ../gh-pages reset origin/gh-pages --hard
+# Update gh-pages before running:
+# git fetch origin gh-pages && git -C ../gh-pages reset origin/gh-pages --hard
 
 # gcc intrinsics
 gcc_intrinsics = set()

diff --git a/main.py b/main.py
@@ -134,8 +134,12 @@ def vadd_mul_sub_w_ev_od(op, desc, even_odd, wide, narrow, narrow2=None):
         narrow_width = widths[narrow]
         signedness = signednesses[narrow]
         signedness2 = signednesses[narrow2]
+        if even_odd == "even":
+            suffix = "ev"
+        else:
+            suffix = "od"
         return instruction(
-            intrinsic=f"__m128i __lsx_v{op}wev_{wide}_{narrow}{intrinsic_suffix} (__m128i a, __m128i b)",
+            intrinsic=f"__m128i __lsx_v{op}w{suffix}_{wide}_{narrow}{intrinsic_suffix} (__m128i a, __m128i b)",
             instr=f"v{op}wev.{wide}.{narrow}{inst_suffix} vr, vr, vr",
             desc=f"{desc} {even_odd}-positioned {signedness} {narrow_width}-bit elements in `a` and {signedness2} elements in `b`, save the {wide_width}-bit result in `dst`.",
         )