Add vsrln

README.md

@@ -6,8 +6,6 @@ Arranged from QEMU implementation and [GCC Intrinsics](https://gcc.gnu.org/onlin
 
 TODO List:
 
-### vsrln.b.h/h.w/w.d
-
 ### vsran.b.h/h.w/w.d
 
 ### vsrlrn.b.h/h.w/w.d

code/gen_impl.py

@@ -121,6 +121,14 @@
                 file=f,
             )
             print(f"}}", file=f)
+        if sign == "s":
+            with open(f"vsrln_{width}_{double_width}.h", "w") as f:
+                print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+                print(
+                    f"  dst.{m}[i] = (i < {64 // w}) ? (u{w})((u{double_w})a.{double_m}[i] >> (b.{double_m}[i] & {double_w-1})) : 0;",
+                    file=f,
+                )
+                print(f"}}", file=f)
 
     if width == "d" or width == "du":
         with open(f"vextl_{double_width}_{width}.h", "w") as f:

code/gen_tb.py

@@ -6,6 +6,7 @@
 widths_all = ["b", "bu", "h", "hu", "w", "wu", "d", "du"]
 widths_vexth = ["h_b", "hu_bu", "w_h", "wu_hu", "d_w", "du_wu", "q_d", "qu_du"]
 widths_vsllwil = ["h_b", "hu_bu", "w_h", "wu_hu", "d_w", "du_wu"]
+widths_vsrln = ["b_h", "h_w", "w_d"]
 widths_vaddw = [
     "h_b",
     "h_bu",
@@ -109,6 +110,7 @@
     "vslei": (widths_all, "v128 a, int imm", [0, 15]),
     "vsrl": (widths_signed, "v128 a, v128 b"),
     "vsrli": (widths_signed, "v128 a, int imm", [0, 7]),
+    "vsrln": (widths_vsrln, "v128 a, v128 b"),
     "vsrlr": (widths_signed, "v128 a, v128 b"),
     "vsrlri": (widths_signed, "v128 a, int imm", [0, 7]),
     "vsra": (widths_signed, "v128 a, v128 b"),

code/vsrln_b_h.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrln_b_h(v128 a, v128 b) {
+  v128 dst;
+#include "vsrln_b_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrln_b_h); }

code/vsrln_b_h.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] = (i < 8) ? (u8)((u16)a.half[i] >> (b.half[i] & 15)) : 0;
+}

code/vsrln_d_q.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] = (i < 1) ? (u64)((u128)a.qword[i] >> (b.qword[i] & 127)) : 0;
+}

code/vsrln_h_w.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrln_h_w(v128 a, v128 b) {
+  v128 dst;
+#include "vsrln_h_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrln_h_w); }

code/vsrln_h_w.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] = (i < 4) ? (u16)((u32)a.word[i] >> (b.word[i] & 31)) : 0;
+}

code/vsrln_w_d.cpp

@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsrln_w_d(v128 a, v128 b) {
+  v128 dst;
+#include "vsrln_w_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsrln_w_d); }

code/vsrln_w_d.h

@@ -0,0 +1,3 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] = (i < 2) ? (u32)((u64)a.dword[i] >> (b.dword[i] & 63)) : 0;
+}

docs/lsx/shift.md

@@ -69,6 +69,10 @@ Compute 128-bit `a` shifted right by `imm * 8` bits.
 {{ vsrli('w') }}
 {{ vsrli('d') }}
 
+{{ vsrln('b', 'h') }}
+{{ vsrln('h', 'w') }}
+{{ vsrln('w', 'd') }}
+
 {{ vsrlr('b') }}
 {{ vsrlr('h') }}
 {{ vsrlr('w') }}

main.py

@@ -1007,4 +1007,14 @@ def vsllwil(name, name2):
             intrinsic=f"__m128i __lsx_vsllwil_{name}_{name2} (__m128i a, imm0_{width2-1} imm)",
             instr=f"vsllwil.{name}.{name2} vr, vr, imm",
             desc=f"Extend and shift {signedness} {width2}-bit elements in `a` by `imm` to {signedness} {width}-bit result.",
+        )
+
+    @env.macro
+    def vsrln(name, name2):
+        width = widths[name[0]]
+        width2 = widths[name2[0]]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vsrln_{name}_{name2} (__m128i a, __m128i b)",
+            instr=f"vsrln.{name}.{name2} vr, vr, vr",
+            desc=f"Logical right shift the unsigned {width2}-bit elements in `a` by elements in `b`, truncate to {width}-bit and store the result to `dst`.",
         )