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Rename verilog-compiler.vhdl to verilog-compiler.yml #1

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Rename verilog-compiler.vhdl to verilog-compiler.yml

Rename verilog-compiler.vhdl to verilog-compiler.yml #1

Workflow file for this run

.github/workflows/verilog-compiler.yml at 52e9688
name: "Verilog Build and Analysis"
on:
[pull_request]
jobs:
build-and-analyze:
runs-on: ubuntu-latest
steps:
- name: Verilog Compiler
uses: jge162/[email protected]
- run: |
echo "Install required dependencies"
sudo apt-get update
sudo apt-get install iverilog
sudo apt-get install verilator
- run: |
echo "Set executable permission on script file"
chmod --recursive +x /*
- run: |
echo "Run, Build Application using script"
VERILOG_FILES=find . -type f -name "*.v" -print0 | xargs -0 echo -n
iverilog -o test_project $VERILOG_FILES