Add advance_cycle

leonardt · Nov 22, 2023 · 66e06c9 · 66e06c9
1 parent 417d213
commit 66e06c9
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/tests/test_property.py b/tests/test_property.py
@@ -951,6 +951,7 @@ class Main(m.Circuit):
     tester.circuit.I = 1
     tester.advance_cycle()
     tester.circuit.I = 0
+    tester.advance_cycle()
     tester.compile_and_run("system-verilog",
                            simulator="ncsim",
                            magma_output="mlir-verilog",