targets/uartbone: Update with LiteX change.

litex-hub · Jul 20, 2023 · ce12166 · ce12166
1 parent 72a9510
commit ce12166
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Showing 6 changed files with 6 additions and 6 deletions.
diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
@@ -141,7 +141,7 @@ def __init__(self, *, sys_clk_freq=100e6, iodelay_clk_freq=200e6,
 
         # UartBone ---------------------------------------------------------------------------------
         if with_uartbone:
-            self.add_uartbone("serial", baudrate=1e6)
+            self.add_uartbone(baudrate=1e6)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:

diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py
@@ -108,7 +108,7 @@ def __init__(self, *, sys_clk_freq=50e6, iodelay_clk_freq=200e6,
 
         # UartBone ---------------------------------------------------------------------------------
         if with_uartbone:
-            self.add_uartbone("serial", baudrate=1e6)
+            self.add_uartbone(baudrate=1e6)
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:

diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py
@@ -196,7 +196,7 @@ def __init__(self, board, revision, sys_clk_freq=60e6, toolchain="trellis",
         if with_uartbone:
             if board != "i5a-907":
                 raise ValueError("uartbone only supported on i5a-907")
-            self.add_uartbone(name="uartbone")
+            self.add_uartbone(uart_name="uartbone")
 
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:

diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py
@@ -98,7 +98,7 @@ def __init__(self, bios_flash_offset, sys_clk_freq=12e6,
         # Add a UARTBone bridge --------------------------------------------------------------------
         debug_uart = False
         if debug_uart:
-            self.add_uartbone(name="serial")
+            self.add_uartbone()
 
 # Flash --------------------------------------------------------------------------------------------
 

diff --git a/litex_boards/targets/mnt_rkx7.py b/litex_boards/targets/mnt_rkx7.py
@@ -183,7 +183,7 @@ def __init__(self, sys_clk_freq=100e6,
         # LiteScope Analyzer -----------------------------------------------------------------------
         if with_analyzer:
             from litescope import LiteScopeAnalyzer
-            self.add_uartbone(name="debug_serial")
+            self.add_uartbone(uart_name="debug_serial")
             analyzer_signals = [
                 ulpi_data.din,
                 utmi.linestate,

diff --git a/litex_boards/targets/terasic_deca.py b/litex_boards/targets/terasic_deca.py
@@ -86,7 +86,7 @@ def __init__(self, sys_clk_freq=50e6,
 
         # UARTbone ---------------------------------------------------------------------------------
         if with_uartbone:
-            self.add_uartbone(name=real_uart_name, baudrate=kwargs["uart_baudrate"])
+            self.add_uartbone(uart_name=real_uart_name, baudrate=kwargs["uart_baudrate"])
 
         # JTAGbone ---------------------------------------------------------------------------------
         if with_jtagbone: