[ot] hw/opentitan: ot_spi_host: SPI Host V3 changes

[rivos-eblot]

SFDP definitions are missing for now, and IRQ tests is still failing.

Moreover the pyot.py configuration needs to be updated (so shall the Bazel rules I guess)

    default:
    {
        rom: ${BASEDIR}/sw/device/silicon_creator/rom/mask_rom_fpga_cw310.elf
        otp: ${BASEDIR}/hw/top_earlgrey/data/otp/img_rma.24.vmem
        # ....
        machine: ot-earlgrey
        embedded-flash: 2
    }
    suffixes:
    [
        _fpga_cw310_rom_with_fake_keys
    ]
    logclass: {
        debug: [
            '^D\\d+'
        ]
        info: [
            '^I\\d+'
        ]
        warning: [
            '^W\\d+'
        ]
        error: [
            '^E\\d+'
        ]
    }
    tests:
    {
        spi_host_smoketest:
        {
            pre:
            [
                ${QEMU_BIN_DIR}/qemu-img create -f raw @{}/spiflash0.raw 16M
            ]
            opts:
            [
                -global ot-earlgrey-board.spiflash0=is25wp128
                -drive if=mtd,id=spiflash,bus=0,format=raw,file=@{}/spiflash0.raw
            ]
            timeout: 10
        }
        spi_host_macronix1Gb_flash_test:
        {
            pre:
            [
                ${QEMU_BIN_DIR}/qemu-img create -f raw @{}/spiflash1.raw 128M
            ]
            opts:
            [
                -global ot-earlgrey-board.spiflash1=mx66l1g45g
                -drive if=mtd,id=spiflash1,bus=1,format=raw,file=@{}/spiflash1.raw
            ]
            timeout: 20
        }
        spi_host_winbond_flash_test:
        {
            pre:
            [
                ${QEMU_BIN_DIR}/qemu-img create -f raw @{}/spiflash0.raw 64M
            ]
            opts:
            [
                -global ot-earlgrey-board.spiflash0=w25q512nw
                -drive if=mtd,id=spiflash0,bus=0,format=raw,file=@{}/spiflash0.raw
            ]
            timeout: 20
        }
        spi_host_irq_test:
        {
            icount: 6
            opts:
            [
                -global ot-spi_host.completion-delay=1000000
            ]
            timeout: 20
        }
   }

[rivos-eblot]

Some progress:

+---------------------------------+--------+----------+--------+-------+
| Name                            | Result |     Time | Icount | Error |
+=================================+========+==========+========+=======+
| spi_host_irq_test               |   FAIL |  6116 ms |        |       |
+---------------------------------+--------+----------+--------+-------+
| spi_host_macronix1Gb_flash_test |   PASS | 12388 ms |        |       |
+---------------------------------+--------+----------+--------+-------+
| spi_host_smoketest              |   PASS |  5892 ms |        |       |
+---------------------------------+--------+----------+--------+-------+
| spi_host_winbond_flash_test     |   PASS | 11804 ms |        |       |
+---------------------------------+--------+----------+--------+-------+

[rivos-eblot]

(stealing PR #119 title)

[rivos-eblot]

spi_host_irq_test will require more work:

1. test results depend on execution on previous tests
2. several tests heavily depend on expected time synchronisation between the host CPU and the HW, which is something that is very hard, if not impossible, to handle with QEMU

spi_host_irq_test test results:

1. spi_host_irq_test.active_event_irq: OK
2. spi_host_irq_test.ready_event_irq OK
3. spi_host_irq_test.tx_empty_event_irq: OK IIF ready_event_irq is not run
4. spi_host_irq_test.tx_wm_event_irq: OK IIF ready_event_irq not run
5. spi_host_irq_test.rx_full_event_irq: FAIL
6. spi_host_irq_test.rx_wm_event_irq: FAIL
7. spi_host_irq_test.cmd_busy_error_irq: OK IIF SPI clock is slow enough

Should be address with another PR; it might be impossible to fix all issues without tweaking the unit tests so that they do not expect a fixed clock ratio between CPU and SPI host.

[rivos-eblot]

@jwnrt you may need to update the Bazel CI files once this PR is merged, as the embedded flash is now using MTD bus # 2 (used to be # 1)

[rivos-eblot]

Note: need to check if the ACTIVE bit implementation has been reworked in the RTL. If used to flicker between each command, rendering it useless from a SW perspective. Maybe this has been fixed, in which case QEMU needs also be fixed.

Update:
6. spi_host_irq_test.rx_full_event_irq: OK
7. spi_host_irq_test.rx_wm_event_irq: OK

[rivos-eblot]

I do not think it is possible to fully pass the spi_host_irq_test for now. If I get it right:

1. The STATUS.active bit goes down between each command. When multiple commands are pushed to the command FIFO, polling this bit alone does not give the information that all commands/transfers have been handled, as the Ibex may poll this bit between each command. To ensure all the commands have completed, the STATUS.cmdqd should be polled for 0 to ensure that all commands, except maybe the last one, have been handled. Only then the STATUS.active bit should be polled. Please let me know if I get it wrong.

2. Tests such cmd_busy_error_irq expect that the Ibex pushes commands faster than the HW can handle them. This may be right for the selected SPI clock and the tight synchronization between the Ibex clock and the peripheral clock on the real HW, but this may not be true on QEMU. It is possible to slow down the SPI execution command on QEMU - so this test passes; however this breaks other tests that have a short timeout, such as tx_wm_event_irq

On my machine (timings may differ from one host to another), it is possible to pass all the spi_host_irq_test tests but the last one ( cmd_busy_error_irq) with this SPI host option: -global ot-spi_host.completion-delay=10000

This PR is ready for review.