[ot] hw/opentitan: ot_spi_host: SPI Host V3 changes

docs/opentitan/earlgrey.md

@@ -96,7 +96,7 @@ See the section "Useful execution options" for documentation about the `no_epmp_
 qemu-system-riscv32 -M ot-earlgrey -display none -serial mon:stdio \
   -object ot-rom_img,id=rom,file=rom_with_fake_keys_fpga_cw310.elf \
   -drive if=pflash,file=otp-rma.raw,format=raw \
-  -drive if=mtd,bus=1,file=flash.raw,format=raw
+  -drive if=mtd,bus=2,file=flash.raw,format=raw
 ````
 
 where `otp-rma.raw` contains the RMA OTP image and `flash.raw` contains the signed binary file of the
@@ -145,14 +145,14 @@ See [`tools.md`](tools.md)
  * `-display none` can be used to prevent QEMU to open a semi-graphical windows as the default
    console, and use the current shell instead.
 
-### Flash
+### Embedded Flash
 
-* `-drive if=mtd,bus=1,file=<filename>,format=raw` should be used to specify a path to a QEMU RAW
-  image file used as the OpenTitan internal flash controller image. This _RAW_ file should have
-  been generated with the [`flashgen.py`](flashgen.md) tool.
+* `-drive if=mtd,id=eflash,bus=2,file=<filename>,format=raw` should be used to specify a path to a
+  QEMU RAW image file used as the OpenTitan internal flash controller image. This _RAW_ file should
+  have been generated with the [`flashgen.py`](flashgen.md) tool.
 
-  Note: for now, bus 1 is assigned to the internal controller with the embedded flash storage. See
-  also SPI Host section.
+  Note: MTD bus 2 is assigned to the internal controller with the embedded flash storage. See also
+  the SPI Host section.
 
 ### OTBN
 
@@ -168,17 +168,21 @@ See [`tools.md`](tools.md)
 
 ### SPI Host
 
+* `-global ot-earlgrey-board.spiflash<bus>=<flash_type>` should be used to instanciate a SPI
+  dataflash device of the specified type to the first device (/CS0) of the specified bus.
+  Any SPI dataflash device supported by QEMU can be used. To list the supported devices, use
+  `grep -F 'INFO("' hw/block/m25p80.c | cut -d'"' -f2`
+
 * `-drive if=mtd,bus=0,file=<filename>,format=raw` should be used to specify a path to a QEMU RAW
-  image file used as the ISSP IS25WP128 SPI data flash backend file. This _RAW_ file should have
-  been created with the qemu-img tool. There is no dedicated tool to populate this image file for
-  now.
+  image file used as the SPI data flash backend file. This _RAW_ file should have been created with
+  the qemu-img tool. There is no dedicated tool to populate this image file for now.
 
   ````sh
   qemu-img create -f raw spi.raw 16M
   ````
 
-  For now, bus 0 is assigned to the SPI Host controller with an external flash storage. See also
-  Flash controller section.
+  MTD bus 0 is assigned to the SPI0 Host controller and MTD bus 1 is assigned to the SPI1 Host
+  controller. See also Embedded Flash controller section.
 
 ### UART
 

hw/block/m25p80.c

@@ -358,6 +358,8 @@ static const FlashPartInfo known_devices[] = {
       .sfdp_read = m25p80_sfdp_w25q512jv },
     { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K),
       .sfdp_read = m25p80_sfdp_w25q01jvq },
+    { INFO("w25q512nw",   0xef6020,      0,  64 << 10, 1024, ER_4K | ER_32K),
+      .sfdp_read = m25p80_sfdp_w25q512nw },
 
     /* Microchip */
     { INFO("25csm04",      0x29cc00,      0x100,  64 << 10,  8, 0) },
@@ -397,6 +399,7 @@ typedef enum {
     DPP = 0xa2,
     QPP = 0x32,
     QPP_4 = 0x34,
+    PP_4 = 0x38,
     RDID_90 = 0x90,
     RDID_AB = 0xab,
     AAI_WP = 0xad,
@@ -751,6 +754,7 @@ static void complete_collecting_data(Flash *s)
     case PP:
     case PP4:
     case PP4_4:
+    case PP_4:
         s->state = STATE_PAGE_PROGRAM;
         break;
     case AAI_WP:
@@ -1150,6 +1154,7 @@ static void decode_new_cmd(Flash *s, uint32_t value)
     case ERASE4_SECTOR:
     case PP:
     case PP4:
+    case PP_4:
     case DIE_ERASE:
     case RDID_90:
     case RDID_AB:

hw/block/m25p80_sfdp.c

@@ -367,6 +367,42 @@ static const uint8_t sfdp_w25q01jvq[] = {
 };
 define_sfdp_read(w25q01jvq);
 
+static const uint8_t sfdp_w25q512nw[] = {
+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
+    0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff,
+    0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x1f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+    0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0x00, 0x33, 0x02, 0xa6, 0x00,
+    0x81, 0xe7, 0x14, 0xd9, 0xe9, 0x63, 0x76, 0x33,
+    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xbd, 0xd5, 0x5c,
+    0x19, 0xf7, 0x5d, 0xff, 0xe9, 0x70, 0xf9, 0xa5,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(w25q512nw);
+
 /*
  * Integrated Silicon Solution (ISSI)
  */

hw/block/m25p80_sfdp.h

@@ -26,6 +26,7 @@ uint8_t m25p80_sfdp_w25q256(uint32_t addr);
 uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
 
 uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
+uint8_t m25p80_sfdp_w25q512nw(uint32_t addr);
 
 uint8_t m25p80_sfdp_is25wp128(uint32_t addr);
 uint8_t m25p80_sfdp_is25wp256(uint32_t addr);