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Darjeeling updates #70
Merged
loiclefort
merged 13 commits into
lowRISC:ot-darjeeling-8.2.0
from
loiclefort:ot-dj-updates-8.2.0
Jul 3, 2024
Merged
Darjeeling updates #70
loiclefort
merged 13 commits into
lowRISC:ot-darjeeling-8.2.0
from
loiclefort:ot-dj-updates-8.2.0
Jul 3, 2024
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…H extension." This is breaking LCOFI and virtual IRQ logic. This reverts commit 1fd02b6.
AIA extends the width of all IRQ CSRs to 64bit even in 32bit systems by adding missing half CSRs. This seems to be missed while adding support for virtual IRQs. The whole logic seems to be correct except the width of the masks. Fixes: 1697837 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5 ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Acked-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> (cherry picked from commit c7fd1e5b89ccf3e75fe28de2aaf93f5f54c724eb https://github.com/alistair23/qemu.git riscv-to-apply.next)
Qemu maps IRQs 0:15 for core interrupts and 16 onward for guest interrupts which are later translated to hgiep in `riscv_cpu_set_irq()` function. With virtual IRQ support added, software now can fully use the whole local interrupt range without any actual hardware attached. This change moves the guest interrupt range after the core local interrupt range to avoid clash. Fixes: 1697837 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5 ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal <[email protected]> Acked-by: Alistair Francis <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Message-ID: <[email protected]> (cherry picked from commit dac40f1f1672d72bbcf1dc3050c2bbdc163076f7 https://github.com/alistair23/qemu.git riscv-to-apply.next)
Currently we assert if we encounter any custom interrupts from 13-63. This change allows forwarding of any custom interrupts. Signed-off-by: Rajnesh Kanwal <[email protected]>
Use a consistent naming scheme across devices Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
…tion. Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
rivos-eblot
approved these changes
Jul 3, 2024
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LGTM, already reviewed internally
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Mainly some clean-up patches to get easier to read memory region names in QEMU monitor + 1 fix for interrupts on
ibexdemo
machine.