Darjeeling updates #70
Commits on Jul 3, 2024
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Revert "[ot] target/riscv: non-standard interrupts are valid without …
…H extension." This is breaking LCOFI and virtual IRQ logic. This reverts commit 1fd02b6.
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FROMGIT: target/riscv: Extend virtual irq csrs masks to be 64 bit wide.
AIA extends the width of all IRQ CSRs to 64bit even in 32bit systems by adding missing half CSRs. This seems to be missed while adding support for virtual IRQs. The whole logic seems to be correct except the width of the masks. Fixes: 1697837 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5 ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Acked-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> (cherry picked from commit c7fd1e5b89ccf3e75fe28de2aaf93f5f54c724eb https://github.com/alistair23/qemu.git riscv-to-apply.next)
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FROMGIT: target/riscv: Move Guest irqs out of the core local irqs range.
Qemu maps IRQs 0:15 for core interrupts and 16 onward for guest interrupts which are later translated to hgiep in `riscv_cpu_set_irq()` function. With virtual IRQ support added, software now can fully use the whole local interrupt range without any actual hardware attached. This change moves the guest interrupt range after the core local interrupt range to avoid clash. Fixes: 1697837 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5 ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal <[email protected]> Acked-by: Alistair Francis <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> Message-ID: <[email protected]> (cherry picked from commit dac40f1f1672d72bbcf1dc3050c2bbdc163076f7 https://github.com/alistair23/qemu.git riscv-to-apply.next)
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[ot] target/riscv: Allow custom interrupts to be forwarded to core.
Currently we assert if we encounter any custom interrupts from 13-63. This change allows forwarding of any custom interrupts. Signed-off-by: Rajnesh Kanwal <[email protected]>
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[ot] hw/opentitan: rename memory region and address space
Use a consistent naming scheme across devices Signed-off-by: Emmanuel Blot <[email protected]>
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[ot] hw/opentitan: ot_sram_ctrl: improve memory region names
Signed-off-by: Emmanuel Blot <[email protected]>
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[ot] hw/riscv: ibex_common: add a dot separator in device names
Signed-off-by: Emmanuel Blot <[email protected]>
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[ot] scripts/opentitan: pyot.py: update ROM image names
Signed-off-by: Emmanuel Blot <[email protected]>
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[ot] .gitlab-ci.d: show clang-format warnings if any
Signed-off-by: Emmanuel Blot <[email protected]>
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[ot] docs/opentitan: rom_ctrl.md: update ROM identifiers
Signed-off-by: Emmanuel Blot <[email protected]>
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[ot] scripts/opentitan: pyot.py: fix an issue when started with no op…
…tion. Signed-off-by: Emmanuel Blot <[email protected]>
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[ot] hw/riscv: ibex_common: add a priority when mapping memory regions
Signed-off-by: Emmanuel Blot <[email protected]>
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[ot] .gitlab-ci.d: update mailbox names and add access range test
Signed-off-by: Emmanuel Blot <[email protected]>
