Merge branch 'pmu-bao-dev'. PMU working in Bao Hypervisor.

.gitignore

@@ -16,3 +16,4 @@ linux_image/
 bao-hypervisor/configs/alsaqr-baremetal/config.S
 bao-hypervisor/configs/alsaqr-linux/config.S
 /fw_payload.elf
+*.debug

bao-baremetal-guest/src/main.c

@@ -57,7 +57,7 @@ void pmu_handler(){
 #define TIMER_WIDTH 8
 #define COUNTER_WIDTH 8
 #define CONFIG_WIDTH 4
-#define NUM_ELEMENT 10
+#define NUM_ELEMENT 1000
 #define PMU_IRQ_ID 143
 
 void read_counters(int num_counter, long long unsigned int BASE_ADDR, int REG_SIZE_IN_BYTES) {
@@ -186,5 +186,13 @@ void main(void){
     printf("cpu %d up\n", get_cpuid());
     spin_unlock(&print_lock);
 
+    volatile uint32_t comp_array[NUM_ELEMENT] = {0};
+    for (int j = 0; j<1000; j++){
+      for (int i=0; i<NUM_ELEMENT; i++) {
+        comp_array[i] = comp_array[i] + i;
+      }
+      printf("Bao bare-metal checkpoint!\n");
+    }
+
     while(1) wfi();
 }

bao-hypervisor/src/arch/riscv/interrupts.c

@@ -24,6 +24,7 @@
 #include <vm.h>
 #include <arch/csrs.h>
 #include <fences.h>
+#include <console.h>
 
 void interrupts_arch_init()
 {
@@ -103,7 +104,10 @@ void interrupts_arch_handle()
             // sbi_set_timer(-1);
             break;
         case SCAUSE_CODE_SEI:
+            CSRC(sie, SIE_SEIE);
             plic_handle();
+            // printk("handled plic interrupt! \n\r");
+            CSRS(sie, SIE_SEIE);
             break;
         default:
             // WARNING("unkown interrupt");

bao-hypervisor/src/core/console.c

@@ -22,10 +22,9 @@
 #include <mem.h>
 #include <fences.h>
 #include <spinlock.h>
+#include <arch/csrs.h>
+
 
-void pmu_v1_interrupt_handler(){
-    printk("PMU interrupt in hypervisor\n\r");
-}
 
 volatile bao_uart_t uart
     __attribute__((section(".devices"), aligned(PAGE_SIZE)));

bao-hypervisor/src/core/inc/console.h

@@ -18,20 +18,6 @@
 
 #include <bao.h>
 
-typedef struct {
-    uint32_t counters[8];
-    uint32_t event_sel[4];
-    uint32_t event_info[4];
-    uint32_t init_budget[8];
-    uint32_t period[2];
-    uint32_t timer[2];
-} __attribute__((__packed__, aligned(PAGE_SIZE))) pmu_v1_global_t;
-
-extern volatile pmu_v1_global_t pmu_v1_global
-    __attribute__((section(".devices")));
-
-void pmu_v1_interrupt_handler();
-
 void console_init();
 void console_write(char const* const str);
 

bao-hypervisor/src/core/inc/pmu_v1.h

@@ -3,6 +3,29 @@
 
 #include <bao.h>
 
+#define PMU_V1_INTR_SRC1 142
+#define PMU_V1_INTR_ID1 (PMU_V1_INTR_SRC1 + 1)
+
+typedef struct {
+    uint32_t counters[8];
+    uint32_t event_sel[4];
+    uint32_t event_info[4];
+    uint32_t init_budget[8];
+    uint32_t period[2];
+    uint32_t timer[2];
+} __attribute__((__packed__, aligned(PAGE_SIZE))) pmu_v1_global_t;
+
+extern volatile pmu_v1_global_t pmu_v1_global
+    __attribute__((section(".devices")));
+
+
+
+
+void pmu_v1_interrupt_handler();
+void pmu_v1_run();
+
+
+
 void pmu_v1_init();
 
 #endif

bao-hypervisor/src/core/init.c

@@ -26,21 +26,7 @@
 #include <arch/csrs.h>
 #include <arch/opcodes.h>
 #include <fences.h>
-
-
-//////////////////////////////////////////////
-
-
-volatile pmu_v1_global_t pmu_v1_global
-    __attribute__((section(".devices")));
-
-
-void pmu_v1_init_localinit(){
-    mem_map_dev(&cpu.as, (void*)&pmu_v1_global, 0x10404000,1);
-    fence_sync_write();
-}
-
-//////////////////////////////////////////////
+#include <pmu_v1.h>
 
 
 
@@ -50,22 +36,6 @@ void init(uint64_t cpu_id, uint64_t load_addr, uint64_t config_addr)
      * These initializations must be executed first and in fixed order.
      */
 
-
-        {
-        unsigned long _stime = CSRR(CSR_TIME);
-        unsigned long _stime2 = CSRR(CSR_TIME);
-        printk("The time is: %lu\r\n", _stime);
-
-        volatile uint32_t comp_array[100] = {0};
-        for (int i=0; i<100; i++) {
-            comp_array[i] = comp_array[i] + i;
-            //printf("Array: %d\r\n", comp_array[i]);
-        }
-
-        _stime2 = CSRR(CSR_TIME);
-        printk("The time is: %lu\r\n", _stime2);
-
-    }
 
 
     cpu_init(cpu_id, load_addr);
@@ -77,13 +47,12 @@ void init(uint64_t cpu_id, uint64_t load_addr, uint64_t config_addr)
         console_init();
         printk("Bao Hypervisor\n\r");
     }
-    printk("Uart page size is: \n\r");
-    pmu_v1_init_localinit();
-    printk("Uart page size is: \n\r");
+    printk("Initializing PMU.... \n\r");
+    pmu_v1_init();
+    printk("PMU initialized! \n\r");
 
     interrupts_init();
 
-
     vmm_init();
 
     /* Should never reach here */

bao-hypervisor/src/core/interrupts.c

@@ -21,6 +21,7 @@
 #include <bitmap.h>
 #include <string.h>
 #include <console.h>
+#include <pmu_v1.h>
 
 BITMAP_ALLOC(hyp_interrupt_bitmap, MAX_INTERRUPTS);
 BITMAP_ALLOC(global_interrupt_bitmap, MAX_INTERRUPTS);
@@ -53,8 +54,8 @@ inline void interrupts_init()
 
     if (cpu.id == CPU_MASTER) {
         interrupts_reserve(IPI_CPU_MSG, cpu_msg_handler);
-        interrupts_reserve(143, pmu_v1_interrupt_handler);
-        interrupts_cpu_enable(143, true);
+        interrupts_reserve(PMU_V1_INTR_ID1, pmu_v1_interrupt_handler);
+        interrupts_cpu_enable(PMU_V1_INTR_ID1, true);
     }
 
     interrupts_cpu_enable(IPI_CPU_MSG, true);

bao-hypervisor/src/core/objects.mk

@@ -25,3 +25,4 @@ core-objs-y+=config.o
 core-objs-y+=console.o
 core-objs-y+=iommu.o
 core-objs-y+=ipc.o
+core-objs-y+=pmu_v1.o

bao-hypervisor/src/core/pmu_v1.c

@@ -7,11 +7,139 @@
 #include <mem.h>
 #include <fences.h>
 #include <spinlock.h>
+#include <printk.h>
+
+// All Widths are in Bytes
+#define NUM_COUNTER 4
+#define COUNTER_WIDTH 8
+#define CONFIG_WIDTH 4
+#define TIMER_WIDTH 8
+
+// For the array traversal
+#define NUM_ELEMENT 100
+
+#define read_32b(addr)         (*(volatile uint32_t *)(long)(addr))
+#define write_32b(addr, val_)  (*(volatile uint32_t *)(long)(addr) = val_)
+
+volatile pmu_v1_global_t pmu_v1_global
+    __attribute__((section(".devices")));
+
+
+void read_32b_regs(uint32_t num_regs, uint64_t base_addr) {
+  uint32_t val;
+  for (uint32_t i=0; i<num_regs; i++) {
+    val = read_32b(base_addr);
+    printk("Read: %x: %x\n", base_addr, val);
+
+    base_addr += 4;
+  }
+}
+
+void write_32b_regs(uint32_t num_regs, uint64_t base_addr, uint32_t val[]) {
+  for (uint32_t i=0; i<num_regs; i++) {
+    write_32b(base_addr, val[i]);
+    printk("Write: %x: %x\n", base_addr, val[i]);
+
+    base_addr += 4;
+  }
+}
+
+void read_64b_regs(uint32_t num_regs, uint64_t base_addr) {
+  uint32_t val_l, val_h;
+  uint64_t val;
+  for (uint32_t i=0; i<num_regs; i++) {
+    val_l = read_32b(base_addr);
+    val_h = read_32b(base_addr+4);
+    val = (uint32_t)((uint64_t)val_h << 32) | val_l;
+    printk("Read: %x: %x\n", base_addr, val);
+
+    base_addr += 8;
+  }
+}
+
+void write_64b_regs(uint32_t num_regs, uint64_t base_addr, uint64_t val[]) {
+  uint32_t val_l, val_h;
+  for (uint32_t i=0; i<num_regs; i++) {
+    val_l = val[i] & 0xFFFFFFFF;
+    val_h = val[i] >> 32;
+    write_32b(base_addr, val_l);
+    write_32b(base_addr+4, val_h);
+    printk("Write: %x: %x\n", base_addr, val[i]);
+
+    base_addr += 8;
+  }
+} 
+
 
 void pmu_v1_init(){
+    mem_map_dev(&cpu.as, (void*)&pmu_v1_global, 0x10404000,1);
+    fence_sync_write();
+}
+
+void pmu_v1_run(){
+    uint64_t PMU_COUNTER_BASE_ADDR      = (uint64_t)&pmu_v1_global;
+    uint64_t PMU_EVENT_SEL_BASE_ADDR    = PMU_COUNTER_BASE_ADDR + 1*NUM_COUNTER*COUNTER_WIDTH + 0*NUM_COUNTER*CONFIG_WIDTH;
+    uint64_t PMU_EVENT_INFO_BASE_ADDR   = PMU_COUNTER_BASE_ADDR + 1*NUM_COUNTER*COUNTER_WIDTH + 1*NUM_COUNTER*CONFIG_WIDTH;
+    uint64_t PMU_INIT_BUDGET_BASE_ADDR  = PMU_COUNTER_BASE_ADDR + 1*NUM_COUNTER*COUNTER_WIDTH + 2*NUM_COUNTER*CONFIG_WIDTH;
+    uint64_t PMU_PERIOD_REG_BASE_ADDR   = PMU_COUNTER_BASE_ADDR + 2*NUM_COUNTER*COUNTER_WIDTH + 2*NUM_COUNTER*CONFIG_WIDTH;
+    uint64_t PMU_TIMER_BASE_ADDR        = PMU_COUNTER_BASE_ADDR + 2*NUM_COUNTER*COUNTER_WIDTH + 2*NUM_COUNTER*CONFIG_WIDTH + 1*TIMER_WIDTH;
+
+    uint64_t counter_val[]      = {0x100, 0x200, 0x300, 0x400};
+    uint32_t event_sel_val[]    = {0x1F002F, 0x1F003F, 0x1F004F, 0x1F005F};
+    uint32_t event_info_val[]   = {0xA00, 0xB00, 0xC00, 0xD00};
+    uint64_t init_budget_val[]  = {0xFFFFFFFFFFFFFFFE, 0xFFFFFA000, 0xFFFFFB000, 0xFFFFFC000};
+    uint64_t period_val[]       = {0x0};
+
+
+
+    printk("Hello PMU!\n");
+
+
+    printk("Counter\n");
+    write_64b_regs(NUM_COUNTER, PMU_COUNTER_BASE_ADDR, counter_val);
+    printk("EventSel Config\n");
+    write_32b_regs(NUM_COUNTER, PMU_EVENT_SEL_BASE_ADDR, event_sel_val);
+    printk("EventInfo Config\n");
+    write_32b_regs(NUM_COUNTER, PMU_EVENT_INFO_BASE_ADDR, event_info_val);
+    printk("Initital Budget\n");
+    write_64b_regs(NUM_COUNTER, PMU_INIT_BUDGET_BASE_ADDR, init_budget_val);
+    printk("Period Register\n");
+    write_64b_regs(1, PMU_PERIOD_REG_BASE_ADDR, period_val);
+    printk("Counters initialized!\n");
+
+    volatile uint32_t comp_array[NUM_ELEMENT] = {0};
+
+    for (uint32_t i=0; i<NUM_ELEMENT; i++) {
+        comp_array[i] = comp_array[i] + i;
+    }
+
+    printk("Array traversed!\n");
+
+
+    printk("Counter\n");
+    read_64b_regs(NUM_COUNTER, PMU_COUNTER_BASE_ADDR);
+    printk("EventSel Config\n");
+    read_32b_regs(NUM_COUNTER, PMU_EVENT_SEL_BASE_ADDR);
+    printk("EventInfo Config\n");
+    read_32b_regs(NUM_COUNTER, PMU_EVENT_INFO_BASE_ADDR);
+    printk("Initital Budget\n");
+    read_64b_regs(NUM_COUNTER, PMU_INIT_BUDGET_BASE_ADDR);
+    printk("Period Register\n");
+    read_64b_regs(1, PMU_PERIOD_REG_BASE_ADDR);
+    printk("Timer Register\n");
+    read_64b_regs(1, PMU_TIMER_BASE_ADDR);
+    printk("The test is over!\n");
+}
+
+void pmu_v1_interrupt_handler(){
+
+    // printk("PMU interrupt in hypervisor\n\r");
 
 }
 
 
 
 
+
+
+