codal_port/ticks_cpu: Check CoreDebug DEMCR trace enable bit. #199
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The DAPLink controlled reset button performs a target reset via SWD, and the CoreDebug trace enable bit seems to be cleared while the DWT->CTRL cycle count enable bit is not. #179 (comment)
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Nice find! I tested this and it fixes the issue. |
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The DAPLink controlled reset button performs a target reset via SWD, and the CoreDebug trace enable bit seems to be cleared while the DWT->CTRL cycle count enable bit is not.
Fixes #179 (comment).