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[DmaToNpu] Add packet support for NpuDmaMemcpyNdOp #785

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Sep 18, 2024
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7 changes: 7 additions & 0 deletions compiler/plugins/target/AMD-AIE/aie/AMDAIEDmaToNpu.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -376,6 +376,13 @@ struct DmaToNpuPattern : OpConversionPattern<NpuDmaMemcpyNdOp> {
// repeat_count
repeat_count = IntegerAttr::get(i32ty, sizes[3] - 1);

// enable_packet
if (auto packetInfo = op.getPacket()) {
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Where is the first place that packet control is turned on?

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@jtuyls jtuyls Sep 18, 2024

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E2E you mean? I have one hacked example working locally that enables it for L3 -> L2 data movement, but I am working on generalizing it.

EDIT: And this is not packet control, but packet routing.

enable_packet = IntegerAttr::get(i32ty, 1);
packet_type = IntegerAttr::get(i32ty, packetInfo->getPktType());
packet_id = IntegerAttr::get(i32ty, packetInfo->getPktId());
}

// Set the issue_token
issue_token = BoolAttr::get(ctx, op.getIssueToken());
// Earlier, all S2MM channels were implicitly assumed to issue a token.
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16 changes: 16 additions & 0 deletions compiler/plugins/target/AMD-AIE/aie/test/dma_to_npu.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -77,3 +77,19 @@ module {
} {sym_name = "explicit_sym_name_0"}
}

// -----

// Issue packet header from shim dma bd
// CHECK: memref.global "public" @toMem : memref<16xi32>
// CHECK: aie.shim_dma_allocation @toMem(S2MM, 0, 0)
// CHECK: npu_instructions = dense_resource<npu_instructions> : tensor<34xui32>, runtime_sequence_name = "packet_enable"
// CHECK: npu_instructions:
module {
aie.device(npu1_4col) {
memref.global "public" @toMem : memref<16xi32>
aiex.runtime_sequence @packet_enable(%arg0: memref<16xi32>) {
aiex.npu.dma_memcpy_nd (0, 0, %arg0[0, 0, 0, 0][1, 1, 16, 16][0, 0, 64, 1], packet = <pkt_id = 2, pkt_type = 3>) { metadata = @toMem, id = 1 : i64 } : memref<16xi32>
}
aie.shim_dma_allocation @toMem (S2MM, 0, 0)
}
}
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