o1vm/riscv32: implement M type instruction divu

o1-labs · Nov 20, 2024 · b44fedc · b44fedc
1 parent d7e039d
commit b44fedc
Showing 1 changed file with 11 additions and 1 deletion.
diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs
@@ -2193,7 +2193,17 @@ pub fn interpret_mtype<Env: InterpreterEnv>(env: &mut Env, instr: MInstruction)
             env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
         }
         MInstruction::Divu => {
-            unimplemented!("Divu")
+            let rs1 = env.read_register(&rs1);
+            let rs2 = env.read_register(&rs2);
+            // FIXME: constrain
+            let res = {
+                let pos = env.alloc_scratch();
+                unsafe { env.div(&rs1, &rs2, pos) }
+            };
+            env.write_register(&rd, res);
+
+            env.set_instruction_pointer(next_instruction_pointer.clone());
+            env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32));
         }
         MInstruction::Rem => {
             let rs1 = env.read_register(&rs1);