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implementation for set less than immediate #2844

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merged 2 commits into from
Dec 17, 2024

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@svv232 svv232 commented Nov 25, 2024

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@svv232 svv232 requested a review from dannywillems November 25, 2024 17:59
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codecov bot commented Nov 26, 2024

Codecov Report

Attention: Patch coverage is 0% with 10 lines in your changes missing coverage. Please review.

Project coverage is 71.99%. Comparing base (ddfc2f6) to head (31f2ab4).
Report is 170 commits behind head on master.

Files with missing lines Patch % Lines
o1vm/src/interpreters/riscv32im/interpreter.rs 0.00% 10 Missing ⚠️
Additional details and impacted files
@@           Coverage Diff            @@
##           master    #2844    +/-   ##
========================================
  Coverage   71.98%   71.99%            
========================================
  Files         256      257     +1     
  Lines       60181    60801   +620     
========================================
+ Hits        43324    43774   +450     
- Misses      16857    17027   +170     

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Base automatically changed from sai/shift_right_arithmetic_immediate to master December 16, 2024 10:00
// slti: x[rd] = (x[rs1] < sext(immediate)) ? 1 : 0
let local_rs1 = env.read_register(&rs1);
let local_imm = env.sign_extend(&imm, 12);
let rd_scratch = env.alloc_scratch();
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Sorry for being picky, but it would be nice to follow the convention of scope for the intermediary variables.

@svv232 svv232 requested a review from dannywillems December 17, 2024 05:42
@dannywillems dannywillems merged commit 04aea4e into master Dec 17, 2024
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@dannywillems dannywillems deleted the sai/set_less_than_immediate_riscv32im branch December 17, 2024 10:58
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2 participants