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8345146: [PPC64] Make intrinsic conversions between bit representations of half precision values and floats #1295

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8345146: [PPC64] Make intrinsic conversions between bit representations of half precision values and floats #1295

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21 changes: 21 additions & 0 deletions src/hotspot/cpu/ppc/assembler_ppc.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -514,13 +514,18 @@ class Assembler : public AbstractAssembler {
LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1),
LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1),

LFIWAX_OPCODE = (31u << OPCODE_SHIFT | 855u << 1),
LFIWZX_OPCODE = (31u << OPCODE_SHIFT | 887u << 1),

STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1),
STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1),
STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1),
STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1),
STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1),
STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1),

STFIWX_OPCODE = (31u << OPCODE_SHIFT | 983u << 1),

FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM
FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM

Expand Down Expand Up @@ -563,6 +568,10 @@ class Assembler : public AbstractAssembler {
XVDIVSP_OPCODE = (60u << OPCODE_SHIFT | 88u << 3),
XXBRD_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 23u << 16), // XX2-FORM
XXBRW_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 15u << 16), // XX2-FORM
XVCVHPSP_OPCODE= (60u << OPCODE_SHIFT | 475u << 2 | 24u << 16), // XX2-FORM
XVCVSPHP_OPCODE= (60u << OPCODE_SHIFT | 475u << 2 | 25u << 16), // XX2-FORM
XSCVHPDP_OPCODE= (60u << OPCODE_SHIFT | 347u << 2 | 16u << 16), // XX2-FORM
XSCVDPHP_OPCODE= (60u << OPCODE_SHIFT | 347u << 2 | 17u << 16), // XX2-FORM
XXPERM_OPCODE = (60u << OPCODE_SHIFT | 26u << 3),
XXSEL_OPCODE = (60u << OPCODE_SHIFT | 3u << 4),
XXSPLTIB_OPCODE= (60u << OPCODE_SHIFT | 360u << 1),
Expand Down Expand Up @@ -2119,6 +2128,9 @@ class Assembler : public AbstractAssembler {
inline void lfdu( FloatRegister d, int si16, Register a);
inline void lfdx( FloatRegister d, Register a, Register b);

inline void lfiwax(FloatRegister d, Register a, Register b);
inline void lfiwzx(FloatRegister d, Register a, Register b);

// PPC 1, section 4.6.3 Floating-Point Store Instructions
inline void stfs( FloatRegister s, int si16, Register a);
inline void stfsu( FloatRegister s, int si16, Register a);
Expand All @@ -2127,6 +2139,8 @@ class Assembler : public AbstractAssembler {
inline void stfdu( FloatRegister s, int si16, Register a);
inline void stfdx( FloatRegister s, Register a, Register b);

inline void stfiwx(FloatRegister s, Register a, Register b);

// PPC 1, section 4.6.4 Floating-Point Move Instructions
inline void fmr( FloatRegister d, FloatRegister b);
inline void fmr_( FloatRegister d, FloatRegister b);
Expand Down Expand Up @@ -2391,6 +2405,10 @@ class Assembler : public AbstractAssembler {
inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void xxbrd( VectorSRegister d, VectorSRegister b);
inline void xxbrw( VectorSRegister d, VectorSRegister b);
inline void xvcvhpsp( VectorSRegister d, VectorSRegister b);
inline void xvcvsphp( VectorSRegister d, VectorSRegister b);
inline void xscvhpdp( VectorSRegister d, VectorSRegister b);
inline void xscvdphp( VectorSRegister d, VectorSRegister b);
inline void xxland( VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void xxsel( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c);
inline void xxspltib( VectorSRegister d, int ui8);
Expand Down Expand Up @@ -2536,10 +2554,13 @@ class Assembler : public AbstractAssembler {
inline void lfsx( FloatRegister d, Register b);
inline void lfd( FloatRegister d, int si16);
inline void lfdx( FloatRegister d, Register b);
inline void lfiwax(FloatRegister d, Register b);
inline void lfiwzx(FloatRegister d, Register b);
inline void stfs( FloatRegister s, int si16);
inline void stfsx( FloatRegister s, Register b);
inline void stfd( FloatRegister s, int si16);
inline void stfdx( FloatRegister s, Register b);
inline void stfiwx(FloatRegister s, Register b);
inline void lvebx( VectorRegister d, Register s2);
inline void lvehx( VectorRegister d, Register s2);
inline void lvewx( VectorRegister d, Register s2);
Expand Down
14 changes: 14 additions & 0 deletions src/hotspot/cpu/ppc/assembler_ppc.inline.hpp
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Expand Up @@ -706,6 +706,9 @@ inline void Assembler::lfd( FloatRegister d, int si16, Register a) { emit_int3
inline void Assembler::lfdu(FloatRegister d, int si16, Register a) { emit_int32( LFDU_OPCODE | frt(d) | ra(a) | simm(si16,16)); }
inline void Assembler::lfdx(FloatRegister d, Register a, Register b) { emit_int32( LFDX_OPCODE | frt(d) | ra0mem(a) | rb(b)); }

inline void Assembler::lfiwax(FloatRegister d, Register a, Register b) { emit_int32( LFIWAX_OPCODE | frt(d) | ra0mem(a) |rb(b)); }
inline void Assembler::lfiwzx(FloatRegister d, Register a, Register b) { emit_int32( LFIWZX_OPCODE | frt(d) | ra0mem(a) |rb(b)); }

// PPC 1, section 4.6.3 Floating-Point Store Instructions
// Use ra0mem instead of ra in some instructions below.
inline void Assembler::stfs( FloatRegister s, int si16, Register a) { emit_int32( STFS_OPCODE | frs(s) | ra0mem(a) | simm(si16,16)); }
Expand All @@ -715,6 +718,8 @@ inline void Assembler::stfd( FloatRegister s, int si16, Register a) { emit_int3
inline void Assembler::stfdu(FloatRegister s, int si16, Register a) { emit_int32( STFDU_OPCODE | frs(s) | ra(a) | simm(si16,16)); }
inline void Assembler::stfdx(FloatRegister s, Register a, Register b){ emit_int32( STFDX_OPCODE | frs(s) | ra0mem(a) | rb(b)); }

inline void Assembler::stfiwx(FloatRegister s, Register a, Register b) { emit_int32( STFIWX_OPCODE | frs(s) | ra0mem(a) |rb(b)); }

// PPC 1, section 4.6.4 Floating-Point Move Instructions
inline void Assembler::fmr( FloatRegister d, FloatRegister b) { emit_int32( FMR_OPCODE | frt(d) | frb(b) | rc(0)); }
inline void Assembler::fmr_(FloatRegister d, FloatRegister b) { emit_int32( FMR_OPCODE | frt(d) | frb(b) | rc(1)); }
Expand Down Expand Up @@ -836,6 +841,10 @@ inline void Assembler::xxlxor( VectorSRegister d, VectorSRegister a, VectorSReg
inline void Assembler::xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXLEQV_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xxbrd( VectorSRegister d, VectorSRegister b) { emit_int32( XXBRD_OPCODE | vsrt(d) | vsrb(b) ); }
inline void Assembler::xxbrw( VectorSRegister d, VectorSRegister b) { emit_int32( XXBRW_OPCODE | vsrt(d) | vsrb(b) ); }
inline void Assembler::xvcvhpsp(VectorSRegister d, VectorSRegister b) { emit_int32( XVCVHPSP_OPCODE | vsrt(d) | vsrb(b) ); }
inline void Assembler::xvcvsphp(VectorSRegister d, VectorSRegister b) { emit_int32( XVCVSPHP_OPCODE | vsrt(d) | vsrb(b) ); }
inline void Assembler::xscvhpdp(VectorSRegister d, VectorSRegister b) { emit_int32( XSCVHPDP_OPCODE | vsrt(d) | vsrb(b) ); }
inline void Assembler::xscvdphp(VectorSRegister d, VectorSRegister b) { emit_int32( XSCVDPHP_OPCODE | vsrt(d) | vsrb(b) ); }
inline void Assembler::xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVDIVSP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVDIVDP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xvabssp( VectorSRegister d, VectorSRegister b) { emit_int32( XVABSSP_OPCODE | vsrt(d) | vsrb(b)); }
Expand Down Expand Up @@ -1130,12 +1139,17 @@ inline void Assembler::lfsx(FloatRegister d, Register b) { emit_int32( LFSX_OPCO
inline void Assembler::lfd( FloatRegister d, int si16) { emit_int32( LFD_OPCODE | frt(d) | simm(si16,16)); }
inline void Assembler::lfdx(FloatRegister d, Register b) { emit_int32( LFDX_OPCODE | frt(d) | rb(b)); }

inline void Assembler::lfiwax(FloatRegister d, Register b) { emit_int32( LFIWAX_OPCODE | frt(d) | rb(b)); }
inline void Assembler::lfiwzx(FloatRegister d, Register b) { emit_int32( LFIWZX_OPCODE | frt(d) | rb(b)); }

// ra0 version
inline void Assembler::stfs( FloatRegister s, int si16) { emit_int32( STFS_OPCODE | frs(s) | simm(si16, 16)); }
inline void Assembler::stfsx(FloatRegister s, Register b) { emit_int32( STFSX_OPCODE | frs(s) | rb(b)); }
inline void Assembler::stfd( FloatRegister s, int si16) { emit_int32( STFD_OPCODE | frs(s) | simm(si16, 16)); }
inline void Assembler::stfdx(FloatRegister s, Register b) { emit_int32( STFDX_OPCODE | frs(s) | rb(b)); }

inline void Assembler::stfiwx(FloatRegister s, Register b) { emit_int32( STFIWX_OPCODE | frs(s) |rb(b)); }

// ra0 version
inline void Assembler::lvebx( VectorRegister d, Register s2) { emit_int32( LVEBX_OPCODE | vrt(d) | rb(s2)); }
inline void Assembler::lvehx( VectorRegister d, Register s2) { emit_int32( LVEHX_OPCODE | vrt(d) | rb(s2)); }
Expand Down
10 changes: 9 additions & 1 deletion src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
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Expand Up @@ -1715,7 +1715,7 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
}


void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
switch (code) {
case lir_sqrt: {
__ fsqrt(dest->as_double_reg(), value->as_double_reg());
Expand All @@ -1725,6 +1725,14 @@ void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, L
__ fabs(dest->as_double_reg(), value->as_double_reg());
break;
}
case lir_f2hf: {
__ f2hf(dest.as_register(), value.as_float_reg(), tmp.as_float_reg());
break;
}
case lir_hf2f: {
__ hf2f(dest->as_float_reg(), value.as_register());
break;
}
default: {
ShouldNotReachHere();
break;
Expand Down
19 changes: 19 additions & 0 deletions src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp
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Expand Up @@ -690,6 +690,25 @@ void LIRGenerator::do_MathIntrinsic(Intrinsic* x) {
__ abs(value.result(), dst, LIR_OprFact::illegalOpr);
break;
}
case vmIntrinsics::_floatToFloat16: {
assert(x->number_of_arguments() == 1, "wrong type");
LIRItem value(x->argument_at(0), this);
value.load_item();
LIR_Opr dst = rlock_result(x);
LIR_Opr tmp = new_register(T_FLOAT);
// f2hf treats tmp as live_in. Workaround: initialize to some value.
__ move(LIR_OprFact::floatConst(-0.0), tmp); // just to satisfy LinearScan
__ f2hf(value.result(), dst, tmp);
break;
}
case vmIntrinsics::_float16ToFloat: {
assert(x->number_of_arguments() == 1, "wrong type");
LIRItem value(x->argument_at(0), this);
value.load_item();
LIR_Opr dst = rlock_result(x);
__ hf2f(value.result(), dst, LIR_OprFact::illegalOpr);
break;
}
case vmIntrinsics::_dsqrt:
case vmIntrinsics::_dsqrt_strict: {
if (VM_Version::has_fsqrt()) {
Expand Down
3 changes: 3 additions & 0 deletions src/hotspot/cpu/ppc/macroAssembler_ppc.hpp
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Expand Up @@ -179,6 +179,9 @@ class MacroAssembler: public Assembler {
void inline set_cmp3(Register dst);
// set dst to (treat_unordered_like_less ? -1 : +1)
void inline set_cmpu3(Register dst, bool treat_unordered_like_less);
// Convert between half precision float encoded into a short and a float in a FloatRegister.
void inline f2hf(Register dst, FloatRegister src, FloatRegister tmp);
void inline hf2f(FloatRegister dst, Register src);

inline void pd_patch_instruction(address branch, address target, const char* file, int line);
NOT_PRODUCT(static void pd_print_patched_instruction(address branch);)
Expand Down
14 changes: 14 additions & 0 deletions src/hotspot/cpu/ppc/macroAssembler_ppc.inline.hpp
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Expand Up @@ -264,6 +264,20 @@ inline void MacroAssembler::set_cmpu3(Register dst, bool treat_unordered_like_le
set_cmp3(dst);
}

inline void MacroAssembler::f2hf(Register dst, FloatRegister src, FloatRegister tmp) {
// Single precision values in FloatRegisters use double precision format on PPC64.
xscvdphp(tmp->to_vsr(), src->to_vsr());
mffprd(dst, tmp);
// Make it a proper short (sign-extended).
extsh(dst, dst);
}

inline void MacroAssembler::hf2f(FloatRegister dst, Register src) {
mtfprd(dst, src);
// Single precision values in FloatRegisters use double precision format on PPC64.
xscvhpdp(dst->to_vsr(), dst->to_vsr());
}

// Convenience bc_far versions
inline void MacroAssembler::blt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, less), L, optimize); }
inline void MacroAssembler::bgt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, greater), L, optimize); }
Expand Down
31 changes: 31 additions & 0 deletions src/hotspot/cpu/ppc/ppc.ad
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Expand Up @@ -2125,6 +2125,9 @@ const bool Matcher::match_rule_supported(int opcode) {
case Op_PopCountI:
case Op_PopCountL:
return (UsePopCountInstruction && VM_Version::has_popcntw());
case Op_ConvF2HF:
case Op_ConvHF2F:
return VM_Version::supports_float16();

case Op_AddVB:
case Op_AddVS:
Expand Down Expand Up @@ -11345,6 +11348,34 @@ instruct convF2D_reg(regD dst, regF src) %{
ins_pipe(pipe_class_default);
%}

instruct convF2HF_reg_reg(iRegIdst dst, regF src, regF tmp) %{
match(Set dst (ConvF2HF src));
effect(TEMP tmp);
ins_cost(3 * DEFAULT_COST);
size(12);
format %{ "xscvdphp $tmp, $src\t# convert to half precision\n\t"
"mffprd $dst, $tmp\t# move result from $tmp to $dst\n\t"
"extsh $dst, $dst\t# make it a proper short"
%}
ins_encode %{
__ f2hf($dst$$Register, $src$$FloatRegister, $tmp$$FloatRegister);
%}
ins_pipe(pipe_class_default);
%}

instruct convHF2F_reg_reg(regF dst, iRegIsrc src) %{
match(Set dst (ConvHF2F src));
ins_cost(2 * DEFAULT_COST);
size(8);
format %{ "mtfprd $dst, $src\t# move source from $src to $dst\n\t"
"xscvhpdp $dst, $dst\t# convert from half precision"
%}
ins_encode %{
__ hf2f($dst$$FloatRegister, $src$$Register);
%}
ins_pipe(pipe_class_default);
%}

//----------Control Flow Instructions------------------------------------------
// Compare Instructions

Expand Down
24 changes: 24 additions & 0 deletions src/hotspot/cpu/ppc/stubGenerator_ppc.cpp
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Expand Up @@ -3557,6 +3557,24 @@ class StubGenerator: public StubCodeGenerator {
return start;
}

address generate_floatToFloat16() {
__ align(CodeEntryAlignment);
StubCodeMark mark(this, "StubRoutines", "floatToFloat16");
address start = __ function_entry();
__ f2hf(R3_RET, F1_ARG1, F0);
__ blr();
return start;
}

address generate_float16ToFloat() {
__ align(CodeEntryAlignment);
StubCodeMark mark(this, "StubRoutines", "float16ToFloat");
address start = __ function_entry();
__ hf2f(F1_RET, R3_ARG1);
__ blr();
return start;
}

address generate_nmethod_entry_barrier() {
__ align(CodeEntryAlignment);
StubCodeMark mark(this, "StubRoutines", "nmethod_entry_barrier");
Expand Down Expand Up @@ -4755,6 +4773,12 @@ class StubGenerator: public StubCodeGenerator {
StubRoutines::_crc32c_table_addr = StubRoutines::ppc::generate_crc_constants(REVERSE_CRC32C_POLY);
StubRoutines::_updateBytesCRC32C = generate_CRC32_updateBytes(true);
}

if (VM_Version::supports_float16()) {
// For results consistency both intrinsics should be enabled.
StubRoutines::_hf2f = generate_float16ToFloat();
StubRoutines::_f2hf = generate_floatToFloat16();
}
}

void generate_continuation_stubs() {
Expand Down
40 changes: 38 additions & 2 deletions src/hotspot/cpu/ppc/templateInterpreterGenerator_ppc.cpp
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Expand Up @@ -1156,6 +1156,44 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
return entry;
}

address TemplateInterpreterGenerator::generate_Float_floatToFloat16_entry() {
if (!VM_Version::supports_float16()) return nullptr;

address entry = __ pc();

__ lfs(F1, Interpreter::stackElementSize, R15_esp);
__ f2hf(R3_RET, F1, F0);

// Restore caller sp for c2i case (from compiled) and for resized sender frame (from interpreted).
__ resize_frame_absolute(R21_sender_SP, R11_scratch1, R0);
__ blr();

__ flush();

return entry;
}

address TemplateInterpreterGenerator::generate_Float_float16ToFloat_entry() {
if (!VM_Version::supports_float16()) return nullptr;

address entry = __ pc();

// Note: Could also use:
//__ li(R3, Interpreter::stackElementSize);
//__ lfiwax(F1_RET, R15_esp, R3); // short stored as 32 bit integer
//__ xscvhpdp(F1_RET->to_vsr(), F1_RET->to_vsr());
__ lwa(R3, Interpreter::stackElementSize, R15_esp);
__ hf2f(F1_RET, R3);

// Restore caller sp for c2i case (from compiled) and for resized sender frame (from interpreted).
__ resize_frame_absolute(R21_sender_SP, R11_scratch1, R0);
__ blr();

__ flush();

return entry;
}

void TemplateInterpreterGenerator::bang_stack_shadow_pages(bool native_call) {
// Quick & dirty stack overflow checking: bang the stack & handle trap.
// Note that we do the banging after the frame is setup, since the exception
Expand Down Expand Up @@ -1936,8 +1974,6 @@ address TemplateInterpreterGenerator::generate_Float_intBitsToFloat_entry() { re
address TemplateInterpreterGenerator::generate_Float_floatToRawIntBits_entry() { return nullptr; }
address TemplateInterpreterGenerator::generate_Double_longBitsToDouble_entry() { return nullptr; }
address TemplateInterpreterGenerator::generate_Double_doubleToRawLongBits_entry() { return nullptr; }
address TemplateInterpreterGenerator::generate_Float_float16ToFloat_entry() { return nullptr; }
address TemplateInterpreterGenerator::generate_Float_floatToFloat16_entry() { return nullptr; }

// =============================================================================
// Exceptions
Expand Down
2 changes: 2 additions & 0 deletions src/hotspot/cpu/ppc/vm_version_ppc.hpp
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Expand Up @@ -97,6 +97,8 @@ class VM_Version: public Abstract_VM_Version {
static bool supports_fast_class_init_checks() { return true; }
constexpr static bool supports_stack_watermark_barrier() { return true; }

static bool supports_float16() { return PowerArchitecturePPC64 >= 9; }

static bool is_determine_features_test_running() { return _is_determine_features_test_running; }
// CPU instruction support
static bool has_fsqrt() { return (_features & fsqrt_m) != 0; }
Expand Down
1 change: 1 addition & 0 deletions test/hotspot/jtreg/compiler/intrinsics/float16/Binary16Conversion.java
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Expand Up @@ -26,6 +26,7 @@
* @bug 8289551 8302976
* @summary Verify conversion between float and the binary16 format
* @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64"
* | ((os.arch == "ppc64" | os.arch == "ppc64le") & vm.cpu.features ~= ".*darn.*")
* @requires vm.compiler1.enabled & vm.compiler2.enabled
* @requires vm.compMode != "Xcomp"
* @comment default run
Expand Down
1 change: 1 addition & 0 deletions test/hotspot/jtreg/compiler/intrinsics/float16/Binary16ConversionNaN.java
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Expand Up @@ -26,6 +26,7 @@
* @bug 8289551 8302976
* @summary Verify NaN sign and significand bits are preserved across conversions
* @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64"
* | ((os.arch == "ppc64" | os.arch == "ppc64le") & vm.cpu.features ~= ".*darn.*")
* @requires vm.compiler1.enabled & vm.compiler2.enabled
* @requires vm.compMode != "Xcomp"
* @library /test/lib /
Expand Down
1 change: 1 addition & 0 deletions test/hotspot/jtreg/compiler/intrinsics/float16/TestAllFloat16ToFloat.java
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Expand Up @@ -26,6 +26,7 @@
* @bug 8302976
* @summary Verify conversion between float and the binary16 format
* @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch == "aarch64"
* | ((os.arch == "ppc64" | os.arch == "ppc64le") & vm.cpu.features ~= ".*darn.*")
* @requires vm.compiler1.enabled & vm.compiler2.enabled
* @requires vm.compMode != "Xcomp"
* @comment default run:
Expand Down
1 change: 1 addition & 0 deletions test/hotspot/jtreg/compiler/intrinsics/float16/TestConstFloat16ToFloat.java
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Expand Up @@ -26,6 +26,7 @@
* @bug 8302976
* @summary Verify conversion cons between float and the binary16 format
* @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64"
* | ((os.arch == "ppc64" | os.arch == "ppc64le") & vm.cpu.features ~= ".*darn.*")
* @requires vm.compiler1.enabled & vm.compiler2.enabled
* @requires vm.compMode != "Xcomp"
* @comment default run:
Expand Down