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    295 repositories

    • chimera

      Public
      Python
      •
      Other
      •2•10•9•1•Updated Nov 28, 2024Nov 28, 2024

    • ManyRVData

      Public
      0•0•0•0•Updated Nov 28, 2024Nov 28, 2024

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •133•379•64•12•Updated Nov 28, 2024Nov 28, 2024

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •2•19•1•3•Updated Nov 28, 2024Nov 28, 2024

    • Deeploy

      Public
      ONNX-to-C Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •9•15•1•3•Updated Nov 28, 2024Nov 28, 2024

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •5•31•0•0•Updated Nov 28, 2024Nov 28, 2024

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •29•98•7•8•Updated Nov 28, 2024Nov 28, 2024

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •48•201•7•19•Updated Nov 28, 2024Nov 28, 2024

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •46•274•3•6•Updated Nov 28, 2024Nov 28, 2024

    • pulp-nnx

      Public
      C
      •
      Apache License 2.0
      •0•3•1•0•Updated Nov 27, 2024Nov 27, 2024

    • dumpling

      Public
      An ATE Pattern Generator for PULP chips and JTAG Taps in general
      Python
      •
      Apache License 2.0
      •2•7•0•1•Updated Nov 27, 2024Nov 27, 2024

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •19•75•1•2•Updated Nov 27, 2024Nov 27, 2024

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •21•58•4•5•Updated Nov 26, 2024Nov 26, 2024

    • parspl

      Public
      0•0•0•0•Updated Nov 26, 2024Nov 26, 2024

    • pulp

      Public
      This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
      SystemVerilog
      •
      Other
      •114•456•26•8•Updated Nov 26, 2024Nov 26, 2024

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •268•1.1k•44•17•Updated Nov 25, 2024Nov 25, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •145•527•31•9•Updated Nov 22, 2024Nov 22, 2024

    • serial_link

      Public
      A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      •
      Other
      •9•20•0•0•Updated Nov 22, 2024Nov 22, 2024

    • common_verification

      Public
      SystemVerilog modules and classes commonly used for verification
      SystemVerilog
      •
      Other
      •13•44•0•4•Updated Nov 22, 2024Nov 22, 2024

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •698•16•1•8•Updated Nov 22, 2024Nov 22, 2024

    • occamy

      Public
      A high-efficiency system-on-chip for floating-point compute workloads.
      Python
      •
      Apache License 2.0
      •13•16•7•1•Updated Nov 21, 2024Nov 21, 2024

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      Other
      •304•7•0•4•Updated Nov 21, 2024Nov 21, 2024

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •22•143•13•5•Updated Nov 21, 2024Nov 21, 2024

    • hero-tools

      Public
      This repository includes a set of software tools enabling heterogeneous OpenMP programming on heterogeneous platforms released by the PULP Project.
      C
      •
      Apache License 2.0
      •0•1•0•0•Updated Nov 19, 2024Nov 19, 2024

    • chimera-sdk

      Public
      Python
      •
      Apache License 2.0
      •2•2•4•0•Updated Nov 15, 2024Nov 15, 2024

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •13•72•13•6•Updated Nov 15, 2024Nov 15, 2024

    • pulp-ethernet

      Public
      SystemVerilog
      •
      Other
      •1•9•0•2•Updated Nov 14, 2024Nov 14, 2024

    • llvm-project

      Public
      12k•6•7•1•Updated Nov 14, 2024Nov 14, 2024

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •34•37•6•4•Updated Nov 13, 2024Nov 13, 2024

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •16•28•4•3•Updated Nov 11, 2024Nov 11, 2024