Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

riscv64: add NOEL-V FPGA target #332

Merged
merged 2 commits into from
Jul 9, 2024
Merged

riscv64: add NOEL-V FPGA target #332

merged 2 commits into from
Jul 9, 2024

Commits on Jul 9, 2024

  1. riscv64: add noelv target

    JIRA: RTOS-844
    lukileczo committed Jul 9, 2024
    Configuration menu
    Copy the full SHA
    1a65b9a View commit details
    Browse the repository at this point in the history
  2. riscv64-generic: fix NULL type definition

    JIRA: RTOS-844
    lukileczo committed Jul 9, 2024
    Configuration menu
    Copy the full SHA
    e66fa86 View commit details
    Browse the repository at this point in the history