riscv64: add NOEL-V FPGA target

hal/riscv64/Makefile

@@ -11,4 +11,4 @@ include hal/riscv64/$(TARGET_SUBFAMILY)/Makefile
 CFLAGS += -Ihal/riscv64/$(TARGET_SUBFAMILY)
 
 OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/, _init.o _interrupts.o _string.o \
-  console.o dtb.o exceptions.o interrupts.o plic.o sbi.o string.o timer.o)
+  dtb.o exceptions.o interrupts.o plic.o sbi.o string.o timer.o)

hal/riscv64/asm-macros.h

@@ -0,0 +1,75 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system loader
+ *
+ * Assembly macros
+ *
+ * Copyright 2024 Phoenix Systems
+ * Author: Lukasz Leczkowski
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+#ifndef _ASM_MACROS_H_
+#define _ASM_MACROS_H_
+
+#define STR(x)  #x
+#define XSTR(x) STR(x)
+
+/* RISC-V registers */
+#define REG_ZERO 0
+#define REG_RA   1
+#define REG_SP   2
+#define REG_GP   3
+#define REG_TP   4
+#define REG_T0   5
+#define REG_T1   6
+#define REG_T2   7
+#define REG_S0   8
+#define REG_S1   9
+#define REG_A0   10
+#define REG_A1   11
+#define REG_A2   12
+#define REG_A3   13
+#define REG_A4   14
+#define REG_A5   15
+#define REG_A6   16
+#define REG_A7   17
+#define REG_S2   18
+#define REG_S3   19
+#define REG_S4   20
+#define REG_S5   21
+#define REG_S6   22
+#define REG_S7   23
+#define REG_S8   24
+#define REG_S9   25
+#define REG_S10  26
+#define REG_S11  27
+#define REG_T3   28
+#define REG_T4   29
+#define REG_T5   30
+#define REG_T6   31
+
+
+#define OPCODE_MISC_MEM 0xf
+#define FUNCT3_CBO      (0x2 << 12)
+
+/* clang-format off */
+
+/* Instructions supported from GCC 14 */
+#define CBO_INVAL(REG) \
+	.word ((REG & 0x1f) << 15) | FUNCT3_CBO | OPCODE_MISC_MEM
+
+#define CBO_CLEAN(REG) \
+	.word (1 << 20) | ((REG & 0x1f) << 15) | FUNCT3_CBO | OPCODE_MISC_MEM
+
+#define CBO_FLUSH(REG) \
+	.word (1 << 21) | ((REG & 0x1f) << 15) | FUNCT3_CBO | OPCODE_MISC_MEM
+
+
+/* clang-format on */
+
+#endif

hal/riscv64/cpu.h

@@ -38,29 +38,42 @@
 #define csr_set(csr, val) \
 	({ \
 		unsigned long __v = (unsigned long)(val); \
-		__asm__ volatile("csrs " #csr ", %0" ::"rK"(__v) : "memory"); \
+		__asm__ volatile ( \
+			"csrs %0, %1" \
+			:: "i"(csr), "rK"(__v) \
+			: "memory"); \
 		__v; \
 	})
 
 
 #define csr_write(csr, val) \
 	({ \
 		unsigned long __v = (unsigned long)(val); \
-		__asm__ volatile("csrw " #csr ", %0" ::"rK"(__v) : "memory"); \
+		__asm__ volatile ( \
+			"csrw %0, %1" \
+			:: "i"(csr), "rK"(__v) \
+			: "memory"); \
 	})
 
 
 #define csr_clear(csr, val) \
 	({ \
 		unsigned long __v = (unsigned long)(val); \
-		__asm__ volatile("csrc " #csr ", %0" ::"rK"(__v) : "memory"); \
+		__asm__ volatile ( \
+			"csrc %0, %1" \
+			::"i"(csr), "rK"(__v) \
+			: "memory"); \
 	})
 
 
 #define csr_read(csr) \
 	({ \
 		register unsigned long __v; \
-		__asm__ volatile("csrr %0, " #csr : "=r"(__v)::"memory"); \
+		__asm__ volatile ( \
+			"csrr %0, %1" \
+			: "=r"(__v) \
+			: "i"(csr) \
+			:"memory"); \
 		__v; \
 	})
 
@@ -74,21 +87,25 @@ static inline void hal_cpuHalt(void)
 
 static inline void hal_cpuDataStoreBarrier(void)
 {
+	__asm__ volatile("fence");
 }
 
 
 static inline void hal_cpuDataMemoryBarrier(void)
 {
+	__asm__ volatile("fence");
 }
 
 
 static inline void hal_cpuDataSyncBarrier(void)
 {
+	__asm__ volatile("fence");
 }
 
 
 static inline void hal_cpuInstrBarrier(void)
 {
+	__asm__ volatile("fence.i");
 }
 
 

hal/riscv64/csr.h

@@ -0,0 +1,39 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system loader
+ *
+ * RV64 CSR definitions
+ *
+ * Copyright 2024 Phoenix Systems
+ * Author: Lukasz Leczkowski
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+#ifndef _CSR_H_
+#define _CSR_H_
+
+/* Unprivileged CSRs */
+
+#define CSR_CYCLE 0xc00u
+#define CSR_TIME  0xc01u
+
+/* Supervisor CSRs */
+
+#define CSR_SSTATUS 0x100u
+#define CSR_SIE     0x104u
+#define CSR_STVEC   0x105u
+
+#define CSR_SENVCFG 0x10au
+
+#define CSR_SSCRATCH 0x140u
+#define CSR_SEPC     0x141u
+#define CSR_SCAUSE   0x142u
+#define CSR_STVAL    0x143u
+#define CSR_SIP      0x144u
+
+
+#endif

hal/riscv64/generic/Makefile

@@ -15,4 +15,4 @@ PLO_COMMANDS ?= alias app blob call console copy dump echo go help kernel map me
 # tty-spike and uart-16550 registers under same major
 PLO_ALLDEVICES := ram-storage tty-spike uart-16550
 
-OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/$(TARGET_SUBFAMILY)/, hal.o)
+OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/$(TARGET_SUBFAMILY)/, console.o hal.o)

hal/riscv64/generic/types.h

@@ -16,7 +16,7 @@
 #ifndef _TYPES_H_
 #define _TYPES_H_
 
-#define NULL 0
+#define NULL ((void *)0)
 
 typedef unsigned char u8;
 typedef unsigned short u16;

hal/riscv64/interrupts.c

@@ -14,14 +14,11 @@
  */
 
 #include "dtb.h"
+#include "csr.h"
 
 #include <hal/hal.h>
 #include <board_config.h>
 
-
-#define STR(x)  #x
-#define XSTR(x) STR(x)
-
 #define CLINT_IRQ_SIZE 16
 
 #define EXT_IRQ 9
@@ -42,10 +39,10 @@ static struct {
 void hal_interruptsEnable(unsigned int irqn)
 {
 	if ((irqn & CLINT_IRQ_FLG) != 0) {
-		csr_set(sie, 1u << (irqn & ~CLINT_IRQ_FLG));
+		csr_set(CSR_SIE, 1u << (irqn & ~CLINT_IRQ_FLG));
 	}
 	else {
-		csr_set(sie, 1u << EXT_IRQ);
+		csr_set(CSR_SIE, 1u << EXT_IRQ);
 		plic_enableInterrupt(1, irqn);
 	}
 }
@@ -54,7 +51,7 @@ void hal_interruptsEnable(unsigned int irqn)
 void hal_interruptsDisable(unsigned int irqn)
 {
 	if ((irqn & CLINT_IRQ_FLG) != 0) {
-		csr_clear(sie, 1u << (irqn & ~CLINT_IRQ_FLG));
+		csr_clear(CSR_SIE, 1u << (irqn & ~CLINT_IRQ_FLG));
 	}
 	else {
 		plic_disableInterrupt(PLIC_SCONTEXT(hal_cpuGetHartId()), irqn);
@@ -64,13 +61,13 @@ void hal_interruptsDisable(unsigned int irqn)
 
 void hal_interruptsEnableAll(void)
 {
-	csr_set(sstatus, SSTATUS_SIE);
+	csr_set(CSR_SSTATUS, SSTATUS_SIE);
 }
 
 
 void hal_interruptsDisableAll(void)
 {
-	csr_clear(sstatus, SSTATUS_SIE);
+	csr_clear(CSR_SSTATUS, SSTATUS_SIE);
 }
 
 
@@ -140,10 +137,10 @@ static int interrupts_setClint(unsigned int n, int (*isr)(unsigned int, void *),
 	interrupts_common.clintHandlers[n].isr = isr;
 
 	if (isr == NULL) {
-		csr_clear(sie, 1u << n);
+		csr_clear(CSR_SIE, 1u << n);
 	}
 	else {
-		csr_set(sie, 1u << n);
+		csr_set(CSR_SIE, 1u << n);
 	}
 
 	return 0;
@@ -185,9 +182,9 @@ void interrupts_init(void)
 		interrupts_common.plicHandlers[i].isr = NULL;
 	}
 
-	csr_write(sscratch, 0);
-	csr_write(sie, -1);
-	csr_write(stvec, _interrupts_dispatch);
+	csr_write(CSR_SSCRATCH, 0);
+	csr_write(CSR_SIE, -1);
+	csr_write(CSR_STVEC, _interrupts_dispatch);
 
 	if (dtb_getPLIC() != 0) {
 		_plic_init();

hal/riscv64/noelv/Makefile

@@ -0,0 +1,17 @@
+#
+# Makefile for Phoenix-RTOS loader (RISC-V 64 NOEL-V HAL)
+#
+# Copyright 2024 Phoenix Systems
+#
+# %LICENSE%
+#
+
+CFLAGS += -DVADDR_KERNEL_INIT=$(VADDR_KERNEL_INIT)
+
+GCCLIB := $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+
+PLO_COMMANDS ?= alias app call console copy dump echo go help kernel map mem phfs reboot script wait
+
+PLO_ALLDEVICES := ram-storage uart-grlib
+
+OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/$(TARGET_SUBFAMILY)/, console.o noelv.o hal.o)

hal/riscv64/noelv/config.h

@@ -0,0 +1,42 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system loader
+ *
+ * Platform configuration
+ *
+ * Copyright 2024 Phoenix Systems
+ * Author: Lukasz Leczkowski
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+#ifndef _CONFIG_H_
+#define _CONFIG_H_
+
+
+#ifndef __ASSEMBLY__
+
+#include "peripherals.h"
+#include "types.h"
+#include "hal/riscv64/cpu.h"
+#include "hal/riscv64/plic.h"
+#include "hal/riscv64/sbi.h"
+#include "hal/riscv64/dtb.h"
+
+#include <phoenix/arch/riscv64/syspage.h>
+#include <phoenix/syspage.h>
+
+#define PATH_KERNEL "phoenix-riscv64-noelv.elf"
+
+#endif /* __ASSEMBLY__ */
+
+#include "noelv.h"
+
+/* Import platform specific definitions */
+#include "ld/riscv64-noelv.ldt"
+
+
+#endif