Skip to content

Commit

Permalink
synth: Refactor synth wrappers
Browse files Browse the repository at this point in the history
  • Loading branch information
@fischeti
fischeti committed Sep 26, 2023
1 parent ca6645d commit 2261738
Show file tree
Hide file tree
Showing 7 changed files with 172 additions and 141 deletions.
3 changes: 2 additions & 1 deletion Bender.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -63,9 +63,10 @@ sources:
- target: any(synthesis,spyglass)
files:
# Level 0
- test/floo_test_pkg.sv
# Level 1
- src/synth/floo_synth_axi_chimney.sv
- src/synth/floo_synth_narrow_wide_chimney.sv
- src/synth/floo_synth_router.sv
- src/synth/floo_synth_router_simple.sv
- src/synth/floo_synth_narrow_wide_router.sv
- src/synth/floo_synth_endpoint.sv
26 changes: 13 additions & 13 deletions src/synth/floo_synth_axi_chimney.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,20 +6,20 @@

module floo_synth_axi_chimney
import floo_pkg::*;
import floo_axi_flit_pkg::*;
import floo_param_pkg::*;
import floo_axi_pkg::*;
import floo_test_pkg::*;
(
input logic clk_i,
input logic rst_ni,
input axi_in_req_t axi_in_req_i,
output axi_in_resp_t axi_in_rsp_o,
output axi_out_req_t axi_out_req_o,
input axi_out_resp_t axi_out_rsp_i,
output axi_in_rsp_t axi_in_rsp_o,
output axi_out_req_t axi_out_req_o,
input axi_out_rsp_t axi_out_rsp_i,
input xy_id_t xy_id_i,
output req_flit_t req_o,
output rsp_flit_t rsp_o,
input req_flit_t req_i,
input rsp_flit_t rsp_i
output floo_req_t floo_req_o,
output floo_rsp_t floo_rsp_o,
input floo_req_t floo_req_i,
input floo_rsp_t floo_rsp_i
);


Expand All @@ -41,10 +41,10 @@ module floo_synth_axi_chimney
.axi_out_rsp_i,
.id_i('0),
.xy_id_i,
.req_o,
.rsp_o,
.req_i,
.rsp_i
.floo_req_o,
.floo_rsp_o,
.floo_req_i,
.floo_rsp_i
);

endmodule
105 changes: 53 additions & 52 deletions src/synth/floo_synth_endpoint.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,46 +6,46 @@

module floo_synth_endpoint
import floo_pkg::*;
import floo_axi_flit_pkg::*;
import floo_param_pkg::*;
import floo_axi_pkg::*;
import floo_test_pkg::*;
(
input logic clk_i,
input logic rst_ni,
input logic test_enable_i,
input axi_in_req_t axi_in_req_i,
output axi_in_resp_t axi_in_rsp_o,
output axi_out_req_t axi_out_req_o,
input axi_out_resp_t axi_out_rsp_i,
output axi_in_rsp_t axi_in_rsp_o,
output axi_out_req_t axi_out_req_o,
input axi_out_rsp_t axi_out_rsp_i,
input xy_id_t xy_id_i,
output req_flit_t [NumRoutes-1:1] req_o,
output rsp_flit_t [NumRoutes-1:1] rsp_o,
input req_flit_t [NumRoutes-1:1] req_i,
input rsp_flit_t [NumRoutes-1:1] rsp_i
output floo_req_t [NumRoutes-1:1] floo_req_o,
output floo_rsp_t [NumRoutes-1:1] floo_rsp_o,
input floo_req_t [NumRoutes-1:1] floo_req_i,
input floo_rsp_t [NumRoutes-1:1] floo_rsp_i
);

req_flit_t chimney_req_in, chimney_req_out;
rsp_flit_t chimney_rsp_in, chimney_rsp_out;
req_data_t [NumRoutes-1:1] req_in, req_out;
rsp_data_t [NumRoutes-1:1] rsp_in, rsp_out;
floo_req_t chimney_req_in, chimney_req_out;
floo_rsp_t chimney_rsp_in, chimney_rsp_out;
floo_req_chan_t [NumRoutes-1:1] req_in, req_out;
floo_rsp_chan_t [NumRoutes-1:1] rsp_in, rsp_out;
logic [NumRoutes-1:1] req_valid_in, req_valid_out;
logic [NumRoutes-1:1] rsp_valid_in, rsp_valid_out;
logic [NumRoutes-1:1] req_ready_in, rsp_ready_in;
logic [NumRoutes-1:1] req_ready_out, rsp_ready_out;


for (genvar i = 1; i < NumRoutes; i++) begin : gen_chimney_req
assign req_o[i].data = req_out[i];
assign rsp_o[i].data = rsp_out[i];
assign req_in[i] = req_i[i].data;
assign rsp_in[i] = rsp_i[i].data;
assign req_valid_in[i] = req_i[i].valid;
assign rsp_valid_in[i] = rsp_i[i].valid;
assign req_ready_in[i] = req_i[i].ready;
assign rsp_ready_in[i] = rsp_i[i].ready;
assign req_o[i].valid = req_valid_out[i];
assign rsp_o[i].valid = rsp_valid_out[i];
assign req_o[i].ready = req_ready_out[i];
assign rsp_o[i].ready = rsp_ready_out[i];
assign floo_req_o[i].req = req_out[i];
assign floo_rsp_o[i].rsp = rsp_out[i];
assign req_in[i] = floo_req_i[i].req;
assign rsp_in[i] = floo_rsp_i[i].rsp;
assign req_valid_in[i] = floo_req_i[i].valid;
assign rsp_valid_in[i] = floo_rsp_i[i].valid;
assign req_ready_in[i] = floo_req_i[i].ready;
assign rsp_ready_in[i] = floo_rsp_i[i].ready;
assign floo_req_o[i].valid = req_valid_out[i];
assign floo_rsp_o[i].valid = rsp_valid_out[i];
assign floo_req_o[i].ready = req_ready_out[i];
assign floo_rsp_o[i].ready = rsp_ready_out[i];
end

floo_axi_chimney #(
Expand All @@ -61,28 +61,29 @@ module floo_synth_endpoint
.clk_i,
.rst_ni,
.test_enable_i,
.sram_cfg_i('0),
.axi_in_req_i,
.axi_in_rsp_o,
.axi_out_req_o,
.axi_out_rsp_i,
.id_i('0),
.xy_id_i,
.req_o(chimney_req_out),
.rsp_o(chimney_rsp_out),
.req_i(chimney_req_in),
.rsp_i(chimney_rsp_in)
);
.floo_req_o(chimney_req_out),
.floo_rsp_o(chimney_rsp_out),
.floo_req_i(chimney_req_in),
.floo_rsp_i(chimney_rsp_in)
);

floo_router #(
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumRoutes ( NumRoutes ),
.flit_t ( req_generic_t ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.RouteAlgo ( XYRouting ),
.IdWidth ( 4 ),
.id_t ( xy_id_t ),
.NumAddrRules ( 1 )
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumRoutes ( NumRoutes ),
.flit_t ( floo_req_generic_flit_t ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.RouteAlgo ( XYRouting ),
.IdWidth ( 4 ),
.id_t ( xy_id_t ),
.NumAddrRules ( 1 )
) i_req_floo_router (
.clk_i,
.rst_ni,
Expand All @@ -91,22 +92,22 @@ module floo_synth_endpoint
.id_route_map_i ('0 ),
.valid_i ( {req_valid_in, chimney_req_out.valid} ),
.ready_o ( {req_ready_out, chimney_req_in.ready} ),
.data_i ( {req_in, chimney_req_out.data} ),
.data_i ( {req_in, chimney_req_out.req} ),
.valid_o ( {req_valid_out, chimney_req_in.valid} ),
.ready_i ( {req_ready_in, chimney_req_out.ready} ),
.data_o ( {req_out, chimney_req_in.data} )
.data_o ( {req_out, chimney_req_in.req} )
);

floo_router #(
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumRoutes ( NumRoutes ),
.flit_t ( rsp_generic_t ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.RouteAlgo ( XYRouting ),
.IdWidth ( 4 ),
.id_t ( xy_id_t ),
.NumAddrRules ( 1 )
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumRoutes ( NumRoutes ),
.flit_t ( floo_rsp_generic_flit_t ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.RouteAlgo ( XYRouting ),
.IdWidth ( 4 ),
.id_t ( xy_id_t ),
.NumAddrRules ( 1 )
) i_rsp_floo_router (
.clk_i,
.rst_ni,
Expand All @@ -115,10 +116,10 @@ module floo_synth_endpoint
.id_route_map_i ('0 ),
.valid_i ( {rsp_valid_in, chimney_rsp_out.valid} ),
.ready_o ( {rsp_ready_out, chimney_rsp_in.ready} ),
.data_i ( {rsp_in, chimney_rsp_out.data} ),
.data_i ( {rsp_in, chimney_rsp_out.rsp} ),
.valid_o ( {rsp_valid_out, chimney_rsp_in.valid} ),
.ready_i ( {rsp_ready_in, chimney_rsp_out.ready} ),
.data_o ( {rsp_out, chimney_rsp_in.data} )
.data_o ( {rsp_out, chimney_rsp_in.rsp} )
);

endmodule
61 changes: 31 additions & 30 deletions src/synth/floo_synth_narrow_wide_chimney.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,26 +6,26 @@

module floo_synth_narrow_wide_chimney
import floo_pkg::*;
import floo_narrow_wide_flit_pkg::*;
import floo_param_pkg::*;
import floo_narrow_wide_pkg::*;
import floo_test_pkg::*;
(
input logic clk_i,
input logic rst_ni,
input narrow_in_req_t narrow_in_req_i,
output narrow_in_resp_t narrow_in_rsp_o,
output narrow_out_req_t narrow_out_req_o,
input narrow_out_resp_t narrow_out_rsp_i,
input wide_in_req_t wide_in_req_i,
output wide_in_resp_t wide_in_rsp_o,
output wide_out_req_t wide_out_req_o,
input wide_out_resp_t wide_out_rsp_i,
input axi_narrow_in_req_t axi_narrow_in_req_i,
output axi_narrow_in_rsp_t axi_narrow_in_rsp_o,
output axi_narrow_out_req_t axi_narrow_out_req_o,
input axi_narrow_out_rsp_t axi_narrow_out_rsp_i,
input axi_wide_in_req_t axi_wide_in_req_i,
output axi_wide_in_rsp_t axi_wide_in_rsp_o,
output axi_wide_out_req_t axi_wide_out_req_o,
input axi_wide_out_rsp_t axi_wide_out_rsp_i,
input xy_id_t xy_id_i,
output narrow_req_flit_t narrow_req_o,
output narrow_rsp_flit_t narrow_rsp_o,
input narrow_req_flit_t narrow_req_i,
input narrow_rsp_flit_t narrow_rsp_i,
output wide_flit_t wide_o,
input wide_flit_t wide_i
output floo_req_t floo_req_o,
output floo_rsp_t floo_rsp_o,
input floo_req_t floo_req_i,
input floo_rsp_t floo_rsp_i,
output floo_wide_t floo_wide_o,
input floo_wide_t floo_wide_i
);


Expand All @@ -50,21 +50,22 @@ floo_narrow_wide_chimney #(
.test_enable_i(1'b0),
.sram_cfg_i('0),
.id_i('0),
.id_map_i ('0),
.xy_id_i,
.narrow_in_req_i,
.narrow_in_rsp_o,
.narrow_out_req_o,
.narrow_out_rsp_i,
.wide_in_req_i,
.wide_in_rsp_o,
.wide_out_req_o,
.wide_out_rsp_i,
.narrow_req_i,
.narrow_rsp_o,
.narrow_req_o,
.narrow_rsp_i,
.wide_o,
.wide_i
.axi_narrow_in_req_i,
.axi_narrow_in_rsp_o,
.axi_narrow_out_req_o,
.axi_narrow_out_rsp_i,
.axi_wide_in_req_i,
.axi_wide_in_rsp_o,
.axi_wide_out_req_o,
.axi_wide_out_rsp_i,
.floo_req_i,
.floo_rsp_o,
.floo_req_o,
.floo_rsp_i,
.floo_wide_o,
.floo_wide_i
);

endmodule
30 changes: 15 additions & 15 deletions src/synth/floo_synth_narrow_wide_router.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,41 +6,41 @@

module floo_synth_narrow_wide_router
import floo_pkg::*;
import floo_narrow_wide_flit_pkg::*;
import floo_param_pkg::*;
import floo_narrow_wide_pkg::*;
import floo_test_pkg::*;
(
input logic clk_i,
input logic rst_ni,
input logic test_enable_i,

input xy_id_t xy_id_i,

input narrow_req_flit_t [NumRoutes-1:0] narrow_req_i,
input narrow_rsp_flit_t [NumRoutes-1:0] narrow_rsp_i,
output narrow_req_flit_t [NumRoutes-1:0] narrow_req_o,
output narrow_rsp_flit_t [NumRoutes-1:0] narrow_rsp_o,
input wide_flit_t [NumRoutes-1:0] wide_i,
output wide_flit_t [NumRoutes-1:0] wide_o
input floo_req_t [NumRoutes-1:0] floo_req_i,
input floo_rsp_t [NumRoutes-1:0] floo_rsp_i,
output floo_req_t [NumRoutes-1:0] floo_req_o,
output floo_rsp_t [NumRoutes-1:0] floo_rsp_o,
input floo_wide_t [NumRoutes-1:0] floo_wide_i,
output floo_wide_t [NumRoutes-1:0] floo_wide_o
);

floo_narrow_wide_router #(
.NumRoutes ( NumRoutes ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.OutputFifoDepth ( OutputFifoDepth ),
.RouteAlgo ( RouteAlgo ),
.RouteAlgo ( XYRouting ),
.id_t ( xy_id_t )
) i_floo_narrow_wide_router (
.clk_i,
.rst_ni,
.test_enable_i,
.xy_id_i,
.id_route_map_i ('0),
.narrow_req_i,
.narrow_req_o,
.narrow_rsp_i,
.narrow_rsp_o,
.wide_i,
.wide_o
.floo_req_i,
.floo_req_o,
.floo_rsp_i,
.floo_rsp_o,
.floo_wide_i,
.floo_wide_o
);

endmodule
Loading

0 comments on commit 2261738

Please sign in to comment.