floogen: Linting

pulp-platform · Sep 13, 2024 · 9cafa53 · 9cafa53
1 parent adc7b13
commit 9cafa53
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Showing 2 changed files with 5 additions and 3 deletions.
diff --git a/floogen/model/protocol.py b/floogen/model/protocol.py
@@ -118,7 +118,7 @@ def req_name(self, port=False, idx=False) -> str:
         """Return the request name of the protocol."""
         idx = self._idx_to_sv_idx() if idx else ""
         if port:
-            return f"{self.base_name}_req_{self.direction[0]}{idx}"
+            return f"{self.base_name}_req_{str(self.direction)[0]}{idx}"
         return f"{self.source}_to_{self.dest}_req"
 
     def rsp_name(self, port=False, idx=False) -> str:

diff --git a/floogen/model/routing.py b/floogen/model/routing.py
@@ -525,8 +525,10 @@ def render_route_cfg(self, name) -> str:
             "RouteAlgo": self.route_algo.value,
             "UseIdTable": bool_to_sv(self.use_id_table),
             "XYAddrOffsetX": self.addr_offset_bits if self.route_algo == RouteAlgo.XY else 0,
-            "XYAddrOffsetY": self.addr_offset_bits + self.num_x_bits if self.route_algo == RouteAlgo.XY else 0,
-            "IdAddrOffset": self.addr_offset_bits if self.route_algo == RouteAlgo.ID and not self.use_id_table else 0,
+            "XYAddrOffsetY": self.addr_offset_bits + self.num_x_bits if
+                                self.route_algo == RouteAlgo.XY else 0,
+            "IdAddrOffset": self.addr_offset_bits if
+                                self.route_algo == RouteAlgo.ID and not self.use_id_table else 0,
             "NumSamRules": len(self.sam),
             "NumRoutes": len(self.table) if self.table is not None else 0,
         }