[SW] Initial support for compilation in Linux environment#312

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mp-17 wants to merge 35 commits intomainfrom mp/sw/os

+2,523-2,164

Commits on Jun 19, 2024

Rename CSRs in ara dispatcher

MaistoV
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Stall Ara upon operations on vector CSRs

MaistoV
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Change "errors" to "exceptions"

MaistoV
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Extend and fix Ara exception reporting from VLSU

MaistoV
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Set vstart=0 for succesful vector instructions

MaistoV
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[hardware] Fix vstart handling in dispatcher
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[hardware] 🐛 Fix reshuffling bug in dispatcher
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[hardware] 🐛 Fix eew_q update during reshuffle
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[hardware] 🐛 Suboptimal fix to reshuffle with LMUL > 1
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[hardware] 🐛 Fix reshuffle
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[hardware] 🐛 Consider LMUL when deciding if to reshuffle vd
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[hardware] Bump CVA6
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Commits on Jun 25, 2024

Refactoring addrgen

MaistoV
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Extensions and bug fixes

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Update submodules

MaistoV
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Supporting vstart CSR for operand read, VALU, VLSU

MaistoV
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tmp commit Adding MMU logic

MaistoV
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tmp commit (MMU stub)

MaistoV
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tmp commit (Extending Ara for MMU stub exceptions

MaistoV
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[hardware] 🐛 Fix end addr computation in addrgen
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[hardware] Support VLD and VST with vstart > 0
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[hardware] 🐛 Flush st-opqueue and reset st-requester upon exception
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[hardware] 🐛 Reshuffle before a vst with vstart > 0
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[hardware] 🐛 Fix packet count hw
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[hardware] 🐛 Fix case when ld exception is not on the first beat
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[hardware] 🐛 Fix case when st exception is not on the first beat
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[hardware] 🐛 Stop Ara frontend until idle after an exception
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[hardware] 🐛 Signal mem op done passing from VLDU and VSTU
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[hardware] 🐛 Don't use vstart to drop elements for slides
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[hardware] 🐛 Fix addr check on AXI transactions
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[hardware] Fix verilator lint
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[hardware] Compress accelerator MMU interface
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[hardware] Fix rebase errors
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[Bender] Bump CVA6
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[apps] Extended sw build for Linux

MaistoV
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mp-17
committed