target/sim: Some cleanup

pulp-platform · Nov 29, 2024 · 0890edb · 0890edb
1 parent b2d9925
commit 0890edb
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Showing 3 changed files with 28 additions and 30 deletions.
diff --git a/.gitignore b/.gitignore
@@ -48,7 +48,6 @@ target/sim/vcs/ucli.key
 target/sim/vcs/work*
 target/sim/vcs/vc_hdrs.h
 
-
 # Xilinx generated files
 target/xilinx/build
 target/xilinx/out

diff --git a/cheshire.mk b/cheshire.mk
@@ -7,8 +7,7 @@
 # Paul Scheffler <[email protected]>
 
 BENDER ?= bender
-
-VLOGAN_BIN ?= vlogan
+VLOGAN ?= vlogan
 
 # Caution: Questasim requires this to point to the *actual* compiler install path
 CXX_PATH := $(shell which $(CXX))
@@ -153,7 +152,7 @@ $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml
 	echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11" -cpppath "$(CXX_PATH)"' >> $@
 
 $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh: $(CHS_ROOT)/Bender.yml
-	$(BENDER) script vcs -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl --vlog-arg="$(VLOGAN_ARGS)" --vlogan-bin="$(VLOGAN_BIN)" > $@
+	$(BENDER) script vcs -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl --vlog-arg="$(VLOGAN_ARGS)" --vlogan-bin="$(VLOGAN)" > $@
 	chmod +x $@
 
 .PRECIOUS: $(CHS_ROOT)/target/sim/models

diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv
@@ -469,7 +469,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   initial begin
     static byte_bt uart_read_buf [$];
     byte_bt bite;
-    string to_print;
+    string line;
     wait_for_reset();
     forever begin
       uart_read_byte(bite);
@@ -478,8 +478,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
         uart_boot_ena = 0;
       end else if (bite == "\n") begin
         if (uart_read_buf.size() > 0) begin
-          to_print = {>>8{uart_read_buf}};
-          $display("[UART] %s", to_print);
+          line = {>>8{uart_read_buf}};
+          $display("[UART] %s", line);
           uart_read_buf.delete();
         end else begin
           $display("[UART]");
@@ -650,7 +650,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
     .AXI_DATA_WIDTH ( DutCfg.AxiDataWidth  ),
     .AXI_ID_WIDTH   ( DutCfg.AxiMstIdWidth ),
     .AXI_USER_WIDTH ( DutCfg.AxiUserWidth  )
-  ) slink_mst_ext(), slink_mst_vip(), slink_mst(), slink_slvs_mux[0:1]();
+  ) slink_mst_ext(), slink_mst_vip(), slink_mst(), slink_slv_mux[1:0]();
 
   AXI_BUS #(
     .AXI_ADDR_WIDTH ( DutCfg.AddrWidth       ),
@@ -668,8 +668,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
     .clk_i  ( clk )
   );
 
-  `AXI_ASSIGN (slink_slvs_mux[0], slink_mst_ext)
-  `AXI_ASSIGN (slink_slvs_mux[1], slink_mst_vip)
+  `AXI_ASSIGN (slink_slv_mux[0], slink_mst_ext)
+  `AXI_ASSIGN (slink_slv_mux[1], slink_mst_vip)
 
   // Multiplex internal and external AXI requests
   axi_mux_intf #(
@@ -683,8 +683,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
     .clk_i  ( clk ),
     .rst_ni ( rst_n ),
     .test_i ( test_mode ),
-    .slv    ( slink_slvs_mux ),
-    .mst    ( slink_mst_mux  )
+    .slv    ( slink_slv_mux ),
+    .mst    ( slink_mst_mux )
   );
 
   // Serialize away added AXI index bits
@@ -956,27 +956,27 @@ endmodule
 
 module vip_cheshire_soc_tristate import cheshire_pkg::*; (
   // I2C pad IO
-  output i2c_sda_i,
-  input  i2c_sda_o,
-  input  i2c_sda_en,
-  output i2c_scl_i,
-  input  i2c_scl_o,
-  input  i2c_scl_en,
+  output wire i2c_sda_i,
+  input  wire i2c_sda_o,
+  input  wire i2c_sda_en,
+  output wire i2c_scl_i,
+  input  wire i2c_scl_o,
+  input  wire i2c_scl_en,
   // SPI host pad IO
-  input                   spih_sck_o,
-  input                   spih_sck_en,
-  input  [SpihNumCs-1:0]  spih_csb_o,
-  input  [SpihNumCs-1:0]  spih_csb_en,
-  output [ 3:0]           spih_sd_i,
-  input  [ 3:0]           spih_sd_o,
-  input  [ 3:0]           spih_sd_en,
+  input  wire                  spih_sck_o,
+  input  wire                  spih_sck_en,
+  input  wire [SpihNumCs-1:0]  spih_csb_o,
+  input  wire [SpihNumCs-1:0]  spih_csb_en,
+  output wire [ 3:0]           spih_sd_i,
+  input  wire [ 3:0]           spih_sd_o,
+  input  wire [ 3:0]           spih_sd_en,
   // I2C wires
-  inout  i2c_sda,
-  inout  i2c_scl,
+  inout  wire i2c_sda,
+  inout  wire i2c_scl,
   // SPI host wires
-  inout                  spih_sck,
-  inout  [SpihNumCs-1:0] spih_csb,
-  inout  [ 3:0]          spih_sd
+  inout  wire                 spih_sck,
+  inout  wire [SpihNumCs-1:0] spih_csb,
+  inout  wire [ 3:0]          spih_sd
 );
 
   // I2C