hyperram: Fix constraints, address map

Signed-off-by: Nils Wistoff <[email protected]>
pulp-platform · May 31, 2024 · 0a6fe6d · 0a6fe6d
1 parent da5f338
commit 0a6fe6d
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Showing 3 changed files with 5 additions and 7 deletions.
diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
@@ -616,7 +616,7 @@ package cheshire_pkg;
     LlcAmoPostCut     : 1,
     LlcOutConnect     : 1,
     LlcOutRegionStart : 'h8000_0000,
-    LlcOutRegionEnd   : 'h1_0000_0000,
+    LlcOutRegionEnd   : 'h8200_0000,
     // VGA: RGB332
     VgaRedWidth       : 3,
     VgaGreenWidth     : 3,

diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc
@@ -23,7 +23,7 @@ set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_50]]
 # Hyperram #
 ############
 
-set period_hyperbus 100
+set period_hyperbus 40
 
 ##  Create RWDS clock (10MHz)
 create_clock -period [expr $period_hyperbus] -name rwds0_clk [get_ports FMC_hyper0_rwds]
@@ -33,10 +33,8 @@ create_clock -period [expr $period_hyperbus] -name rwds1_clk [get_ports FMC_hype
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets iobuf_rwds1_i/O]
 
 ## Create the PHY clock
-create_generated_clock [get_nets i_hyperbus/clk_phy_i_0] \
-                       -name clk_phy -source [get_pins i_clkwiz/clk_50] -divide_by 2
-create_generated_clock [get_nets i_hyperbus/clk_phy_i_90] \
-                       -name clk_phy_90 -source [get_pins i_clkwiz/clk_50] -edges {2 4 6}
+create_generated_clock [get_pins i_hyperbus/clock_generator.ddr_clk/clk0_o] -name clk_phy -source [get_pins i_clkwiz/clk_50] -divide_by 2
+create_generated_clock [get_pins i_hyperbus/clock_generator.ddr_clk/clk90_o] -name clk_phy_90 -source [get_pins i_clkwiz/clk_50] -edges {2 4 6}
 
 ## PHY0
 set clk_rx_shift [expr $period_hyperbus/10]

diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv
@@ -107,7 +107,7 @@ module cheshire_top_xilinx (
     ret.RegExtNumRules        = 1;
     ret.RegExtRegionIdx   [0] = 0;
     ret.RegExtRegionStart [0] = 'h4000_0000;
-    ret.RegExtRegionEnd   [0] = 'h6000_0000;
+    ret.RegExtRegionEnd   [0] = 'h4010_0000;
     return ret;
   endfunction