treewide: Connect LLC performance counters to cheshire regs
GitHub Actions / verible-verilog-lint
failed
Apr 18, 2024 in 0s
reviewdog [verible-verilog-lint] report
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Findings (2)
hw/cheshire_soc.sv|569 col 101| Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
hw/cheshire_soc.sv|570 col 101| Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 569 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L569
Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:569 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 570 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L570
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:570 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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