FPU: Bump to pulp-v0.1.1 (#25)

* Bump FPU to pulp-v0.1.1 * Remove vendor folder in CVFPU * Update Bender.lock * cvfpu: Exclude util directory Signed-off-by: Nils Wistoff <[email protected]> * Bender.lock: Revert unrelated changes Signed-off-by: Nils Wistoff <[email protected]> --------- Signed-off-by: Nils Wistoff <[email protected]> Co-authored-by: Nils Wistoff <[email protected]> Signed-off-by: Nils Wistoff <[email protected]>
pulp-platform · Sep 26, 2024 · 6ee486e · 6ee486e
1 parent 7e9fcfd
commit 6ee486e
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Showing 21 changed files with 58 additions and 13 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -39,7 +39,8 @@
 	url = https://github.com/openhwgroup/core-v-verif
 [submodule "core/cvfpu"]
 	path = core/cvfpu
-	url = https://github.com/openhwgroup/cvfpu.git
+	url = https://github.com/pulp-platform/cvfpu.git
+	branch = pulp-v0.1.1
 [submodule "core/cache_subsystem/hpdcache"]
 	path = core/cache_subsystem/hpdcache
 	url = https://github.com/paulsc96/cv-hpdcache.git

diff --git a/Bender.yml b/Bender.yml
@@ -10,7 +10,7 @@ dependencies:
   axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.31.0 }
   common_cells:
     { git: "https://github.com/pulp-platform/common_cells", version: 1.23.0 }
-  fpnew: { git: "https://github.com/openhwgroup/cvfpu.git", version: 0.7.0 }
+  fpnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: pulp-v0.1.1 }
   tech_cells_generic:
     { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 }
 

diff --git a/core/cvfpu b/core/cvfpu
diff --git a/core/fpu_wrap.sv b/core/fpu_wrap.sv
@@ -64,7 +64,9 @@ module fpu_wrap
         Width: unsigned'(CVA6Cfg.FLen),  // parameterized using CVA6Cfg.FLen
         EnableVectors: CVA6Cfg.XFVec,
         EnableNanBox: 1'b1,
-        FpFmtMask: {CVA6Cfg.RVF, CVA6Cfg.RVD, CVA6Cfg.XF16, CVA6Cfg.XF8, CVA6Cfg.XF16ALT},
+        FpFmtMask: {
+          CVA6Cfg.RVF, CVA6Cfg.RVD, CVA6Cfg.XF16, CVA6Cfg.XF8, CVA6Cfg.XF16ALT, CVA6Cfg.XF8ALT
+        },
         IntFmtMask: {
           CVA6Cfg.XFVec && CVA6Cfg.XF8,
           CVA6Cfg.XFVec && (CVA6Cfg.XF16 || CVA6Cfg.XF16ALT),
@@ -75,24 +77,27 @@ module fpu_wrap
 
     // Implementation (number of registers etc)
     localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
-        PipeRegs: '{  // FP32, FP64, FP16, FP8, FP16alt
+        PipeRegs: '{  // FP32, FP64, FP16, FP8, FP16alt, FP8alt
             '{
                 unsigned'(LAT_COMP_FP32),
                 unsigned'(LAT_COMP_FP64),
                 unsigned'(LAT_COMP_FP16),
                 unsigned'(LAT_COMP_FP8),
-                unsigned'(LAT_COMP_FP16ALT)
+                unsigned'(LAT_COMP_FP16ALT),
+                unsigned'(LAT_COMP_FP8ALT)
             },  // ADDMUL
             '{default: unsigned'(LAT_DIVSQRT)},  // DIVSQRT
             '{default: unsigned'(LAT_NONCOMP)},  // NONCOMP
-            '{default: unsigned'(LAT_CONV)}
-        },  // CONV
+            '{default: unsigned'(LAT_CONV)},  // CONV
+            '{default: unsigned'(LAT_SDOTP)}
+        },  // DOTP
         UnitTypes: '{
             '{default: fpnew_pkg::PARALLEL},  // ADDMUL
             '{default: fpnew_pkg::MERGED},  // DIVSQRT
             '{default: fpnew_pkg::PARALLEL},  // NONCOMP
-            '{default: fpnew_pkg::MERGED}
-        },  // CONV
+            '{default: fpnew_pkg::MERGED},  // CONV
+            '{default: fpnew_pkg::DISABLED}
+        },  // DOTP
         PipeConfig: fpnew_pkg::DISTRIBUTED
     };
 
@@ -535,6 +540,7 @@ module fpu_wrap
     ) i_fpnew_bulk (
         .clk_i,
         .rst_ni,
+        .hart_id_i     ('0),
         .operands_i    (fpu_operands),
         .rnd_mode_i    (fpnew_pkg::roundmode_e'(fpu_rm)),
         .op_i          (fpnew_pkg::operation_e'(fpu_op)),
@@ -544,7 +550,7 @@ module fpu_wrap
         .int_fmt_i     (fpnew_pkg::int_format_e'(fpu_ifmt)),
         .vectorial_op_i(fpu_vec_op),
         .tag_i         (fpu_tag),
-        .simd_mask_i   (1'b1),
+        .simd_mask_i   ('1),
         .in_valid_i    (fpu_in_valid),
         .in_ready_o    (fpu_in_ready),
         .flush_i,

diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv
@@ -50,9 +50,11 @@ package ariane_pkg;
   localparam int unsigned LAT_COMP_FP16 = 'd1;
   localparam int unsigned LAT_COMP_FP16ALT = 'd1;
   localparam int unsigned LAT_COMP_FP8 = 'd1;
+  localparam int unsigned LAT_COMP_FP8ALT = 'd1;
   localparam int unsigned LAT_DIVSQRT = 'd2;
   localparam int unsigned LAT_NONCOMP = 'd1;
   localparam int unsigned LAT_CONV = 'd2;
+  localparam int unsigned LAT_SDOTP = 'd2;
 
   localparam logic [31:0] OPENHWGROUP_MVENDORID = 32'h0602;
   localparam logic [31:0] ARIANE_MARCHID = 32'd3;

diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv
@@ -3,20 +3,22 @@ package build_config_pkg;
   function automatic config_pkg::cva6_cfg_t build_config(config_pkg::cva6_user_cfg_t CVA6Cfg);
     bit IS_XLEN32 = (CVA6Cfg.XLEN == 32) ? 1'b1 : 1'b0;
     bit IS_XLEN64 = (CVA6Cfg.XLEN == 32) ? 1'b0 : 1'b1;
-    bit FpPresent = CVA6Cfg.RVF | CVA6Cfg.RVD | CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8;
-    bit NSX = CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8 | CVA6Cfg.XFVec;  // Are non-standard extensions present?
+    bit FpPresent = CVA6Cfg.RVF | CVA6Cfg.RVD | CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8 | CVA6Cfg.XF8ALT;
+    bit NSX = CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8 | CVA6Cfg.XF8ALT | CVA6Cfg.XFVec;  // Are non-standard extensions present?
     int unsigned FLen = CVA6Cfg.RVD ? 64 :  // D ext.
     CVA6Cfg.RVF ? 32 :  // F ext.
     CVA6Cfg.XF16 ? 16 :  // Xf16 ext.
     CVA6Cfg.XF16ALT ? 16 :  // Xf16alt ext.
     CVA6Cfg.XF8 ? 8 :  // Xf8 ext.
+    CVA6Cfg.XF8ALT ? 8 :  // Xf8alt ext.
     1;  // Unused in case of no FP
 
     // Transprecision floating-point extensions configuration
     bit RVFVec     = CVA6Cfg.RVF     & CVA6Cfg.XFVec & FLen>32; // FP32 vectors available if vectors and larger fmt enabled
     bit XF16Vec    = CVA6Cfg.XF16    & CVA6Cfg.XFVec & FLen>16; // FP16 vectors available if vectors and larger fmt enabled
     bit XF16ALTVec = CVA6Cfg.XF16ALT & CVA6Cfg.XFVec & FLen>16; // FP16ALT vectors available if vectors and larger fmt enabled
     bit XF8Vec     = CVA6Cfg.XF8     & CVA6Cfg.XFVec & FLen>8;  // FP8 vectors available if vectors and larger fmt enabled
+    bit XF8ALTVec  = CVA6Cfg.XF8ALT  & CVA6Cfg.XFVec & FLen>8;  // FP8ALT vectors available if vectors and larger fmt enabled
 
     bit EnableAccelerator = CVA6Cfg.RVV;  // Currently only used by V extension (Ara)
     int unsigned NrWbPorts = (CVA6Cfg.CvxifEn || EnableAccelerator) ? 5 : 4;
@@ -62,6 +64,7 @@ package build_config_pkg;
     cfg.XF16 = CVA6Cfg.XF16;
     cfg.XF16ALT = CVA6Cfg.XF16ALT;
     cfg.XF8 = CVA6Cfg.XF8;
+    cfg.XF8ALT = CVA6Cfg.XF8ALT;
     cfg.RVA = CVA6Cfg.RVA;
     cfg.RVB = CVA6Cfg.RVB;
     cfg.RVV = CVA6Cfg.RVV;
@@ -84,6 +87,7 @@ package build_config_pkg;
     cfg.XF16Vec = bit'(XF16Vec);
     cfg.XF16ALTVec = bit'(XF16ALTVec);
     cfg.XF8Vec = bit'(XF8Vec);
+    cfg.XF8ALTVec = bit'(XF8ALTVec);
     // Can take 2 or 3 in single issue. 4 or 6 in dual issue.
     cfg.NrRgprPorts = unsigned'(CVA6Cfg.SuperscalarEn ? 4 : 2);
     // cfg.NrRgprPorts = unsigned'(CVA6Cfg.SuperscalarEn ? 6 : 3);

diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv
@@ -78,6 +78,8 @@ package config_pkg;
     bit                          XF16ALT;
     // Non standard 8bits Floating Point extension
     bit                          XF8;
+    // TO_BE_COMPLETED
+    bit                          XF8ALT;
     // Non standard Vector Floating Point extension
     bit                          XFVec;
     // Perf counters
@@ -233,6 +235,7 @@ package config_pkg;
     bit          XF16;
     bit          XF16ALT;
     bit          XF8;
+    bit          XF8ALT;
     bit          RVA;
     bit          RVB;
     bit          RVV;
@@ -256,6 +259,7 @@ package config_pkg;
     bit          XF16Vec;
     bit          XF16ALTVec;
     bit          XF8Vec;
+    bit          XF8ALTVec;
     int unsigned NrRgprPorts;
     int unsigned NrWbPorts;
     bit          EnableAccelerator;

diff --git a/core/include/cv32a60x_config_pkg_deprecated.sv b/core/include/cv32a60x_config_pkg_deprecated.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 1;
@@ -90,6 +91,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv
@@ -15,6 +15,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 1;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 0;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 0;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 0;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 0;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 1;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 0;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 1;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
@@ -23,6 +23,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 1;
@@ -96,6 +97,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 0;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 1;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 1;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 1;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),

diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
@@ -16,6 +16,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigF16En = 0;
   localparam CVA6ConfigF16AltEn = 0;
   localparam CVA6ConfigF8En = 0;
+  localparam CVA6ConfigF8AltEn = 0;
   localparam CVA6ConfigFVecEn = 0;
 
   localparam CVA6ConfigCvxifEn = 0;
@@ -89,6 +90,7 @@ package cva6_config_pkg;
       XF16: bit'(CVA6ConfigF16En),
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
+      XF8ALT: bit'(CVA6ConfigF8AltEn),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
+16 −0		Bender.yml
+201 −0		LICENSE.apache
+0 −0		LICENSE.solderpad
+5 −0		README.license.md
+32 −8		README.md
+20 −0		docs/CHANGELOG-PULP.md
+5 −0		docs/CHANGELOG.md
+53 −18		docs/README.md
+7 −1		src/fpnew_cast_multi.sv
+476 −0		src/fpnew_divsqrt_th_32.sv
+7 −1		src/fpnew_fma.sv
+7 −1		src/fpnew_fma_multi.sv
+11 −3		src/fpnew_opgroup_block.sv
+45 −25		src/fpnew_opgroup_fmt_slice.sv
+216 −54		src/fpnew_opgroup_multifmt_slice.sv
+97 −16		src/fpnew_pkg.sv
+46 −3		src/fpnew_rounding.sv
+1,444 −0		src/fpnew_sdotp_multi.sv
+190 −0		src/fpnew_sdotp_multi_wrapper.sv
+13 −4		src/fpnew_top.sv
+352 −0		src/lfsr_sr.sv
+15 −0		src_files.yml
+5 −0		util/README.md
+782 −0		util/vendor.py
+14 −0		vendor/opene906.lock.hjson
+50 −0		vendor/opene906.vendor.hjson
+50 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v
+783 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v
+163 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ff1.v
+275 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_pack_single.v
+286 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v
+540 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_round_single.v
+345 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_special.v
+824 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_srt_single.v
+461 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_top.v
+299 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_dp.v
+90 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_frbus.v
+92 −0		vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_src_type.v
+201 −0		vendor/opene906/LICENSE
+75 −0		vendor/opene906/README.md
+31 −0		vendor/patches/opene906/0001-Patch-pa_fdsu_prepare.patch
+589 −0		vendor/patches/opene906/0001-Patch-pa_fpu_fp.patch
+375 −0		vendor/patches/opene906/0001-Patch-pa_fpu_frbus.patch