fixup! fixup! coherence: Pack Valid/Dirty SRAM (#36)

Signed-off-by: Nils Wistoff <[email protected]>
pulp-platform · Sep 26, 2024 · ae42c74 · ae42c74
1 parent c3a24c1
commit ae42c74
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Showing 6 changed files with 8 additions and 11 deletions.
diff --git a/Makefile b/Makefile
@@ -99,11 +99,7 @@ endif
 # cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv32a6_ima_sv32_fpga
 # Changing the default target to cv32a60x for Step1 verification
 target     ?= cv64a6_imafdc_sv39
-ifeq ($(target), cv64a6_imafdc_sv39)
-	XLEN ?= 64
-else
-	XLEN ?= 32
-endif
+XLEN ?= 64
 ifndef TARGET_CFG
 	export TARGET_CFG = $(target)
 endif

diff --git a/core/cache_subsystem/hpdcache b/core/cache_subsystem/hpdcache
diff --git a/corev_apu/fpga/src/bootrom/Makefile b/corev_apu/fpga/src/bootrom/Makefile
@@ -1,5 +1,5 @@
 XLEN ?= 64
-CROSSCOMPILE ?= riscv-none-elf-
+CROSSCOMPILE ?= riscv64-unknown-elf-
 
 ifeq ($(BOARD), nexys_video)
 DRAM_SIZE_64 ?= 0x20000000 #512MB

diff --git a/corev_apu/tb/ariane_tb.cpp b/corev_apu/tb/ariane_tb.cpp
@@ -333,7 +333,7 @@ int main(int argc, char **argv) {
 #if (VERILATOR_VERSION_INTEGER >= 5000000)
   // Verilator v5: Use rootp pointer and .data() accessor.
 #define MEM top->rootp->ariane_testharness__DOT__i_sram__DOT__i_tc_sram__DOT__sram.m_storage
-#define MEM_USER top->rootp->ariane_testharness__DOT__i_sram__DOT__gen_mem_user__DOT__itc_sram__DOT__sram.m_storage
+#define MEM_USER top->rootp->ariane_testharness__DOT__i_sram__DOT__gen_mem_user__DOT__i_tc_sram__DOT__sram.m_storage
 #else
   // Verilator v4
 #define MEM top->ariane_testharness__DOT__i_sram__DOT__i_tc_sram__DOT__sram

diff --git a/verif/regress/dv-riscv-arch-test.sh b/verif/regress/dv-riscv-arch-test.sh
@@ -15,7 +15,7 @@ if ! [ -n "$RISCV" ]; then
 fi
 
 # install the required tools
-source ./verif/regress/install-verilator.sh
+#source ./verif/regress/install-verilator.sh
 source ./verif/regress/install-spike.sh
 source verif/regress/install-riscv-arch-test.sh
 
@@ -36,4 +36,5 @@ else
 fi
 
 cd verif/sim
+echo "python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld"
 python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py
@@ -1126,7 +1126,7 @@ def check_cc_version():
 
   cc_path = get_env_var("RISCV_CC")
   cc_version = run_cmd(f"{cc_path} --version")
-  cc_version_string = cc_version.split("\n")[0].split(" ")[2]
+  cc_version_string = cc_version.split("\n")[0].split(" ")[3]
   cc_version_number = re.split(r'\D+', cc_version_string)
 
   logging.info(f"GCC Version: {cc_version_string}")
@@ -1283,7 +1283,7 @@ def main():
         # Join the list back into a string
         args.iss = ','.join(args_list)
 
-    check_tools_version()
+    # check_tools_version()
 
     # create file handler which logs even debug messages13.1.1
     fh = logging.FileHandler('logfile.log')