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Create a dataflow-oriented descriptor-based iDMA frontend supporting …
…prefetching - tracer: Add WIP version of the iDMA tracer (#9), add some fixes (#14) - frontends/desc64: Transition Regbus master to AXI master - jobs.json: Add descriptor-based testbench to the job file - frontends/desc64: Update synth module for descriptor frontend - test/frontends: Add testbench for benchmarking (***caution: not to be used as VIP***) - frontends/desc64: Remove unused shared counter - Makefile: Quote paths to handle spaces in paths - frontends/desc64: Add prefetching design
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,24 @@ | ||
| # Copyright 2022 ETH Zurich and University of Bologna. | ||
| # Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| # SPDX-License-Identifier: SHL-0.51 | ||
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| # Axel Vanoni <[email protected]> | ||
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| source scripts/compile_vsim.tcl | ||
| vsim tb_idma_desc64_bench -t 1ps \ | ||
| -GNumberOfTests=150 \ | ||
| -GChainedDescriptors=20 \ | ||
| -GSimulationTimeoutCycles=300000 \ | ||
| -GTransferLength=24 \ | ||
| -GDoIRQ=0 \ | ||
| +trace_file=trace-test.log \ | ||
| -voptargs=+acc | ||
| #-voptargs=-pedantic | ||
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| set StdArithNoWarnings 1 | ||
| set NumericStdNoWarnings 1 | ||
| log -r /* | ||
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| source scripts/waves/vsim_fe_desc64.do | ||
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| run -all |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,22 @@ | ||
| # Copyright 2022 ETH Zurich and University of Bologna. | ||
| # Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| # SPDX-License-Identifier: SHL-0.51 | ||
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| # Axel Vanoni <[email protected]> | ||
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| # run frontend tests without chaining | ||
| source scripts/compile_vsim.tcl | ||
| vsim tb_idma_desc64_top -t 1ps \ | ||
| -GNumberOfTests=20 \ | ||
| -GMaxChainedDescriptors=1 \ | ||
| -GSimulationTimeoutCycles=2000 \ | ||
| -voptargs=+acc | ||
| #-voptargs=-pedantic | ||
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| set StdArithNoWarnings 1 | ||
| set NumericStdNoWarnings 1 | ||
| log -r /* | ||
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| source scripts/waves/vsim_fe_desc64.do | ||
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| run -all |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,21 @@ | ||
| # Copyright 2022 ETH Zurich and University of Bologna. | ||
| # Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| # SPDX-License-Identifier: SHL-0.51 | ||
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| # Axel Vanoni <[email protected]> | ||
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| # run frontend tests with one transfer | ||
| source scripts/compile_vsim.tcl | ||
| vsim tb_idma_desc64_top -t 1ps -GNumberOfTests=1 \ | ||
| -GSimulationTimeoutCycles=200 \ | ||
| -GMaxChainedDescriptors=1 \ | ||
| -voptargs=+acc | ||
| #-voptargs=-pedantic | ||
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| set StdArithNoWarnings 1 | ||
| set NumericStdNoWarnings 1 | ||
| log -r /* | ||
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| source scripts/waves/vsim_fe_desc64.do | ||
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| run -all |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,23 @@ | ||
| # Copyright 2022 ETH Zurich and University of Bologna. | ||
| # Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| # SPDX-License-Identifier: SHL-0.51 | ||
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| # Axel Vanoni <[email protected]> | ||
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| # run tests with only chaining | ||
| source scripts/compile_vsim.tcl | ||
| vsim tb_idma_desc64_top -t 1ps \ | ||
| -GMaxChainedDescriptors=100 \ | ||
| -GMinChainedDescriptors=100 \ | ||
| -GSimulationTimeoutCycles=2000 \ | ||
| -GNumberOfTests=1 \ | ||
| -voptargs=+acc | ||
| #-voptargs=-pedantic | ||
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| set StdArithNoWarnings 1 | ||
| set NumericStdNoWarnings 1 | ||
| log -r /* | ||
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| source scripts/waves/vsim_fe_desc64.do | ||
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| run -all |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,18 @@ | ||
| # Copyright 2022 ETH Zurich and University of Bologna. | ||
| # Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| # SPDX-License-Identifier: SHL-0.51 | ||
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| # Axel Vanoni <[email protected]> | ||
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| # run frontend tests with default settings | ||
| source scripts/compile_vsim.tcl | ||
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| vsim tb_idma_desc64_top -t 1ps -voptargs=+acc | ||
| #-voptargs=-pedantic | ||
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| source scripts/waves/vsim_fe_desc64.do | ||
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| set StdArithNoWarnings 1 | ||
| set NumericStdNoWarnings 1 | ||
| log -r /* | ||
| run -all |
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| @@ -0,0 +1,17 @@ | ||
| onerror {resume} | ||
| quietly WaveActivateNextPane {} 0 | ||
| add wave -position end i_dut/clk_i | ||
| add wave -position end i_dut/rst_ni | ||
| add wave -position end i_dut/master_req_o | ||
| add wave -position end i_dut/master_rsp_i | ||
| add wave -position end i_dut/slave_req_i | ||
| add wave -position end i_dut/slave_rsp_o | ||
| add wave -position end i_dut/idma_req_o | ||
| add wave -position end i_dut/idma_req_ready_i | ||
| add wave -position end i_dut/idma_req_valid_o | ||
| add wave -position end i_dut/idma_rsp_ready_o | ||
| add wave -position end i_dut/idma_rsp_valid_i | ||
| add wave -position end i_dut/idma_busy_i | ||
| add wave -position end i_dut/irq_o | ||
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| quietly wave cursor active 1 |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,132 @@ | ||
| // Copyright 2022 ETH Zurich and University of Bologna. | ||
| // Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| // SPDX-License-Identifier: SHL-0.51 | ||
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| // Axel Vanoni <[email protected]> | ||
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| `include "common_cells/assertions.svh" | ||
| `include "common_cells/registers.svh" | ||
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| /// This module generates AR packets to fetch descriptors from memory | ||
| module idma_desc64_ar_gen #( | ||
| /// AXI Data width | ||
| parameter int unsigned DataWidth = 64, | ||
| /// Descriptor type. `$bits(descriptor_t)` must be a power of two | ||
| parameter type descriptor_t = logic, | ||
| /// AXI AR channel type | ||
| parameter type axi_ar_chan_t = logic, | ||
| /// AXI AR id type | ||
| parameter type axi_id_t = logic, | ||
| /// Type that can hold the usage information of the idma_req fifo | ||
| parameter type usage_t = logic, | ||
| /// AXI Address type | ||
| parameter type addr_t = logic | ||
| )( | ||
| /// Clock | ||
| input logic clk_i, | ||
| /// Reset | ||
| input logic rst_ni, | ||
| /// AXI AR channel | ||
| output axi_ar_chan_t axi_ar_chan_o, | ||
| /// AXI AR valid | ||
| output logic axi_ar_chan_valid_o, | ||
| /// AXI AR ready | ||
| input logic axi_ar_chan_ready_i, | ||
| /// AXI ID to use when requesting | ||
| input axi_id_t axi_ar_id_i, | ||
| /// queued address to use when we reach the last in a chain | ||
| input addr_t queued_address_i, | ||
| /// queued address valid | ||
| input logic queued_address_valid_i, | ||
| /// queued address ready | ||
| output logic queued_address_ready_o, | ||
| /// next address as read from descriptor | ||
| input addr_t next_address_from_descriptor_i, | ||
| /// next address valid | ||
| input logic next_address_from_descriptor_valid_i, | ||
| /// number of available slots in the idma request fifo | ||
| input usage_t idma_req_available_slots_i, | ||
| /// address for feedback for the next request | ||
| output addr_t feedback_addr_o, | ||
| /// feedback address valid | ||
| output logic feedback_addr_valid_o, | ||
| /// whether the unit is busy | ||
| output logic busy_o | ||
| ); | ||
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| `define MIN(a, b) ((a) < (b) ? a : b) | ||
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| localparam int unsigned DataWidthBytes = DataWidth / 8; | ||
| localparam int unsigned DescriptorSize = $bits(descriptor_t) / 8; | ||
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| localparam logic [2:0] AxiSize = `MIN(`MIN($clog2(DataWidthBytes), | ||
| $clog2(DescriptorSize)), 3'b111); | ||
| localparam logic [7:0] AxiLength = DescriptorSize / DataWidthBytes - 1; | ||
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| logic inflight_q, inflight_d; | ||
| logic next_addr_from_desc_valid_q, next_addr_from_desc_valid_d; | ||
| logic next_addr_from_desc_valid_this_cycle; | ||
| logic take_from_queued; | ||
| logic may_send_ar; | ||
| addr_t next_addr_q, next_addr_d; | ||
| addr_t ar_addr; | ||
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| assign next_addr_from_desc_valid_d = next_address_from_descriptor_valid_i; | ||
| assign next_addr_from_desc_valid_this_cycle = !next_addr_from_desc_valid_q && | ||
| next_address_from_descriptor_valid_i; | ||
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| assign next_addr_d = next_addr_from_desc_valid_this_cycle ? | ||
| next_address_from_descriptor_i : | ||
| next_addr_q; | ||
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| assign take_from_queued = (next_addr_from_desc_valid_this_cycle ? | ||
| next_address_from_descriptor_i == '1 : | ||
| next_addr_q == '1); | ||
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| assign ar_addr = take_from_queued ? queued_address_i : | ||
| (next_addr_from_desc_valid_this_cycle ? | ||
| next_address_from_descriptor_i : next_addr_q); | ||
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| assign may_send_ar = idma_req_available_slots_i > 0 && | ||
| (!inflight_q || next_addr_from_desc_valid_this_cycle); | ||
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| always_comb begin : proc_inflight | ||
| inflight_d = inflight_q; | ||
| if (axi_ar_chan_ready_i && axi_ar_chan_valid_o) begin | ||
| inflight_d = 1'b1; | ||
| end else if (next_addr_from_desc_valid_this_cycle) begin | ||
| inflight_d = 1'b0; | ||
| end | ||
| end | ||
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| always_comb begin : proc_ready_valid | ||
| axi_ar_chan_valid_o = 1'b0; | ||
| queued_address_ready_o = 1'b0; | ||
| if (may_send_ar) begin | ||
| if (take_from_queued) begin | ||
| axi_ar_chan_valid_o = queued_address_valid_i; | ||
| queued_address_ready_o = axi_ar_chan_ready_i; | ||
| end else begin | ||
| axi_ar_chan_valid_o = 1'b1; | ||
| end | ||
| end | ||
| end | ||
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| always_comb begin : proc_ar | ||
| axi_ar_chan_o = '0; | ||
| axi_ar_chan_o.id = axi_ar_id_i; | ||
| axi_ar_chan_o.addr = ar_addr; | ||
| axi_ar_chan_o.len = AxiLength; | ||
| axi_ar_chan_o.size = AxiSize; | ||
| axi_ar_chan_o.burst = axi_pkg::BURST_INCR; | ||
| end | ||
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| `FF(inflight_q, inflight_d, 1'b0); | ||
| `FF(next_addr_from_desc_valid_q, next_addr_from_desc_valid_d, 1'b0); | ||
| `FF(next_addr_q, next_addr_d, '1); | ||
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| assign feedback_addr_o = ar_addr; | ||
| assign feedback_addr_valid_o = axi_ar_chan_ready_i && axi_ar_chan_valid_o; | ||
| assign busy_o = !take_from_queued || inflight_q; | ||
|
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| endmodule : idma_desc64_ar_gen |
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