Create a dataflow-oriented descriptor-based iDMA frontend supporting …

…prefetching - tracer: Add WIP version of the iDMA tracer (#9), add some fixes (#14) - frontends/desc64: Transition Regbus master to AXI master - jobs.json: Add descriptor-based testbench to the job file - frontends/desc64: Update synth module for descriptor frontend - test/frontends: Add testbench for benchmarking (***caution: not to be used as VIP***) - frontends/desc64: Remove unused shared counter - Makefile: Quote paths to handle spaces in paths - frontends/desc64: Add prefetching design
pulp-platform · Oct 31, 2022 · 23bedba · 23bedba
1 parent 4456785
commit 23bedba
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Showing 32 changed files with 3,122 additions and 935 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -71,3 +71,13 @@ tiny-dma-run:
         job: prepare-non-free
     strategy: depend
 
+frontend-descriptor-run:
+  stage: iDMA
+  needs:
+    - prepare-non-free
+  trigger:
+    include:
+      - artifact: idma-non-free/ci/gitlab-frontend-descriptor-ci.yml
+        job: prepare-non-free
+    strategy: depend
+
diff --git a/Bender.lock b/Bender.lock
@@ -1,7 +1,7 @@
 packages:
   axi:
-    revision: 9a53b3c66d32725e5c5656b02e1caf07c5f79a97
-    version: 0.37.0
+    revision: a25b415958e83e232096aa3863da56887abd5991
+    version: 0.39.0-beta
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -17,14 +17,14 @@ packages:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: 5def6fee3f010b603357d7b941661892aeafcc5d
-    version: 0.2.2
+    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
+    version: 0.2.3
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   register_interface:
-    revision: 1e23b79db80cb89b4d27fdbd10776df33d6a2ff4
-    version: 0.3.3
+    revision: d59b4f1c77469dcb23f370f32769af309c4add6a
+    version: 0.3.4
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:

diff --git a/Bender.yml b/Bender.yml
@@ -11,7 +11,7 @@ package:
 dependencies:
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.26.0 }
   common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.2 }
-  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.37.0 }
+  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0-beta }
   register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 }
 
 export_include_dirs:
@@ -61,13 +61,23 @@ sources:
 
   - files: # 64bit descriptor frontend
     # Level 0
+    - src/frontends/desc64/idma_desc64_synth_pkg.sv
+    - src/frontends/desc64/idma_desc64_ar_gen.sv
+    - src/frontends/desc64/idma_desc64_ar_gen_prefetch.sv
+    - src/frontends/desc64/idma_desc64_reader.sv
+    - src/frontends/desc64/idma_desc64_reader_gater.sv
     - src/frontends/desc64/idma_desc64_reg_pkg.sv
     - src/frontends/desc64/idma_desc64_reg_top.sv
-    - src/frontends/desc64/idma_desc64_shared_counter.sv
+    - src/frontends/desc64/idma_desc64_reshaper.sv
     # Level 1
     - src/frontends/desc64/idma_desc64_reg_wrapper.sv
     # Level 2
     - src/frontends/desc64/idma_desc64_top.sv
+    - src/systems/cva6_desc/dma_desc_wrap.sv
+    - src/systems/cva6_desc/dma_desc_synth_pkg.sv
+    - src/systems/cva6_desc/dma_desc_synth.sv
+    # Level 3
+    - src/frontends/desc64/idma_desc64_synth.sv
 
   # Systems
   - target: all(pulp, not(mchan))
@@ -99,3 +109,4 @@ sources:
     files:
       # Level 0
       - test/frontends/tb_idma_desc64_top.sv
+      - test/frontends/tb_idma_desc64_bench.sv
diff --git a/Makefile b/Makefile
@@ -146,7 +146,7 @@ VLT_ARGS  += --no-skip-identical
 VLT_TOP   ?=
 
 verilator/files_raw.txt: Bender.yml Bender.lock
-	$(BENDER) script verilator -t synthesis > $@
+	$(BENDER) script verilator -t synthesis -t pulp -t cva6 > $@
 
 verilator/files.txt: verilator/scripts/preprocess.py verilator/files_raw.txt
 	$(PYTHON) $^ > $@
@@ -291,39 +291,39 @@ REG_HTML_STRING = "<!DOCTYPE html>\n<html>\n<head>\n<link rel="stylesheet" href=
 gen_regs: reg32_2d_regs reg64_regs desc64_regs
 
 reg32_2d_regs:
-	$(PYTHON) $(REG_TOOL) $(REG32_2D_HJSON) -t $(REG32_2D_FE_DIR) -r
-	$(PYTHON) $(REG_TOOL) $(REG32_2D_HJSON) -D > $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.h
-	printf $(REG_HTML_STRING) > $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.html
-	$(PYTHON) $(REG_TOOL) $(REG32_2D_HJSON) -d >> $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.html
-	printf "</html>\n" >> $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.html
-	cp $(REG_PATH)/vendor/lowrisc_opentitan/util/reggen/reg_html.css $(REG32_2D_FE_DIR)
+	"$(PYTHON)" "$(REG_TOOL)" "$(REG32_2D_HJSON)" -t "$(REG32_2D_FE_DIR)" -r
+	"$(PYTHON)" "$(REG_TOOL)" "$(REG32_2D_HJSON)" -D > "$(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.h"
+	printf $(REG_HTML_STRING) > "$(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.html"
+	"$(PYTHON)" "$(REG_TOOL)" "$(REG32_2D_HJSON)" -d >> "$(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.html"
+	printf "</html>\n" >> "$(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.html"
+	cp "$(REG_PATH)/vendor/lowrisc_opentitan/util/reggen/reg_html.css" "$(REG32_2D_FE_DIR)"
 
 reg64_regs:
-	$(PYTHON) $(REG_TOOL) $(REG64_HJSON) -t $(REG64_FE_DIR) -r
-	$(PYTHON) $(REG_TOOL) $(REG64_HJSON) -D > $(REG64_FE_DIR)/idma_reg64_frontend.h
-	printf $(REG_HTML_STRING) > $(REG64_FE_DIR)/idma_reg64_frontend.html
-	$(PYTHON) $(REG_TOOL) $(REG64_HJSON) -d >> $(REG64_FE_DIR)/idma_reg64_frontend.html
-	printf "</html>\n" >> $(REG64_FE_DIR)/idma_reg64_frontend.html
-	cp $(REG_PATH)/vendor/lowrisc_opentitan/util/reggen/reg_html.css $(REG64_FE_DIR)
+	"$(PYTHON)" "$(REG_TOOL)" "$(REG64_HJSON)" -t "$(REG64_FE_DIR)" -r
+	"$(PYTHON)" "$(REG_TOOL)" "$(REG64_HJSON)" -D > "$(REG64_FE_DIR)/idma_reg64_frontend.h"
+	printf $(REG_HTML_STRING) > "$(REG64_FE_DIR)/idma_reg64_frontend.html"
+	"$(PYTHON)" "$(REG_TOOL)" "$(REG64_HJSON)" -d >> "$(REG64_FE_DIR)/idma_reg64_frontend.html"
+	printf "</html>\n" >> "$(REG64_FE_DIR)/idma_reg64_frontend.html"
+	cp "$(REG_PATH)/vendor/lowrisc_opentitan/util/reggen/reg_html.css" "$(REG64_FE_DIR)"
 
 desc64_regs:
-	$(PYTHON) $(REG_TOOL) $(DESC64_HJSON) -t $(DESC64_FE_DIR) -r
-	$(PYTHON) $(REG_TOOL) $(DESC64_HJSON) -D > $(DESC64_FE_DIR)/idma_desc64_frontend.h
-	printf $(REG_HTML_STRING) > $(DESC64_FE_DIR)/idma_desc64_frontend.html
-	$(PYTHON) $(REG_TOOL) $(DESC64_HJSON) -d >> $(DESC64_FE_DIR)/idma_desc64_frontend.html
-	printf "</html>\n" >> $(DESC64_FE_DIR)/idma_desc64_frontend.html
-	cp $(REG_PATH)/vendor/lowrisc_opentitan/util/reggen/reg_html.css $(DESC64_FE_DIR)
+	"$(PYTHON)" "$(REG_TOOL)" "$(DESC64_HJSON)" -t "$(DESC64_FE_DIR)" -r
+	"$(PYTHON)" "$(REG_TOOL)" "$(DESC64_HJSON)" -D > "$(DESC64_FE_DIR)/idma_desc64_frontend.h"
+	printf $(REG_HTML_STRING) > "$(DESC64_FE_DIR)/idma_desc64_frontend.html"
+	"$(PYTHON)" "$(REG_TOOL)" "$(DESC64_HJSON)" -d >> "$(DESC64_FE_DIR)/idma_desc64_frontend.html"
+	printf "</html>\n" >> "$(DESC64_FE_DIR)/idma_desc64_frontend.html"
+	cp "$(REG_PATH)/vendor/lowrisc_opentitan/util/reggen/reg_html.css" "$(DESC64_FE_DIR)"
 
 regs_clean:
-	rm -f $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.h
-	rm -f $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend_reg_pkg.sv
-	rm -f $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend_reg_top.sv
-	rm -f $(REG32_2D_FE_DIR)/reg_html.css
-	rm -f $(REG64_FE_DIR)/idma_reg64_frontend.h
-	rm -f $(REG64_FE_DIR)/idma_reg32_frontend_reg_pkg.sv
-	rm -f $(REG64_FE_DIR)/idma_reg32_frontend_reg_top.sv
-	rm -f $(REG64_FE_DIR)/reg_html.css
-	rm -f $(DESC64_FE_DIR)/idma_desc64_frontend.h
-	rm -f $(DESC64_FE_DIR)/idma_desc64_reg_pkg.sv
-	rm -f $(DESC64_FE_DIR)/idma_desc64_reg_top.sv
-	rm -f $(DESC64_FE_DIR)/reg_html.css
+	rm -f "$(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.h"
+	rm -f "$(REG32_2D_FE_DIR)/idma_reg32_2d_frontend_reg_pkg.sv"
+	rm -f "$(REG32_2D_FE_DIR)/idma_reg32_2d_frontend_reg_top.sv"
+	rm -f "$(REG32_2D_FE_DIR)/reg_html.css"
+	rm -f "$(REG64_FE_DIR)/idma_reg64_frontend.h"
+	rm -f "$(REG64_FE_DIR)/idma_reg32_frontend_reg_pkg.sv"
+	rm -f "$(REG64_FE_DIR)/idma_reg32_frontend_reg_top.sv"
+	rm -f "$(REG64_FE_DIR)/reg_html.css"
+	rm -f "$(DESC64_FE_DIR)/idma_desc64_frontend.h"
+	rm -f "$(DESC64_FE_DIR)/idma_desc64_reg_pkg.sv"
+	rm -f "$(DESC64_FE_DIR)/idma_desc64_reg_top.sv"
+	rm -f "$(DESC64_FE_DIR)/reg_html.css"
diff --git a/jobs.json b/jobs.json
@@ -79,5 +79,17 @@
         "synth_top" : "idma_nd_backend_synth",
         "overrides" : {
         }
+    },
+    "frontend-descriptor": {
+        "seed" : 1336,
+        "man_jobs" : {
+            "simple" : "/dev/null"
+        },
+        "gen_jobs" : {
+        },
+        "testbench" : "tb_idma_desc64_top",
+        "synth_top" : "idma_desc64_synth",
+        "overrides" : {
+        }
     }
 }
diff --git a/scripts/frontend/bench.tcl b/scripts/frontend/bench.tcl
@@ -0,0 +1,24 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+# Axel Vanoni <[email protected]>
+
+source scripts/compile_vsim.tcl
+vsim tb_idma_desc64_bench -t 1ps \
+    -GNumberOfTests=150 \
+    -GChainedDescriptors=20 \
+    -GSimulationTimeoutCycles=300000 \
+    -GTransferLength=24 \
+    -GDoIRQ=0 \
+    +trace_file=trace-test.log \
+    -voptargs=+acc
+#-voptargs=-pedantic
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+log -r /*
+
+source scripts/waves/vsim_fe_desc64.do
+
+run -all
diff --git a/scripts/frontend/run-no-chain.tcl b/scripts/frontend/run-no-chain.tcl
@@ -0,0 +1,22 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+# Axel Vanoni <[email protected]>
+
+# run frontend tests without chaining
+source scripts/compile_vsim.tcl
+vsim tb_idma_desc64_top -t 1ps \
+    -GNumberOfTests=20 \
+    -GMaxChainedDescriptors=1 \
+    -GSimulationTimeoutCycles=2000 \
+    -voptargs=+acc
+#-voptargs=-pedantic
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+log -r /*
+
+source scripts/waves/vsim_fe_desc64.do
+
+run -all
diff --git a/scripts/frontend/run-one.tcl b/scripts/frontend/run-one.tcl
@@ -0,0 +1,21 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+# Axel Vanoni <[email protected]>
+
+# run frontend tests with one transfer
+source scripts/compile_vsim.tcl
+vsim tb_idma_desc64_top -t 1ps -GNumberOfTests=1 \
+    -GSimulationTimeoutCycles=200 \
+    -GMaxChainedDescriptors=1 \
+    -voptargs=+acc
+#-voptargs=-pedantic
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+log -r /*
+
+source scripts/waves/vsim_fe_desc64.do
+
+run -all
diff --git a/scripts/frontend/run-only-chain.tcl b/scripts/frontend/run-only-chain.tcl
@@ -0,0 +1,23 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+# Axel Vanoni <[email protected]>
+
+# run tests with only chaining
+source scripts/compile_vsim.tcl
+vsim tb_idma_desc64_top -t 1ps \
+    -GMaxChainedDescriptors=100 \
+    -GMinChainedDescriptors=100 \
+    -GSimulationTimeoutCycles=2000 \
+    -GNumberOfTests=1 \
+    -voptargs=+acc
+#-voptargs=-pedantic
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+log -r /*
+
+source scripts/waves/vsim_fe_desc64.do
+
+run -all
diff --git a/scripts/frontend/run.tcl b/scripts/frontend/run.tcl
@@ -0,0 +1,18 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+# Axel Vanoni <[email protected]>
+
+# run frontend tests with default settings
+source scripts/compile_vsim.tcl
+
+vsim tb_idma_desc64_top -t 1ps -voptargs=+acc
+#-voptargs=-pedantic
+
+source scripts/waves/vsim_fe_desc64.do
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+log -r /*
+run -all
diff --git a/scripts/verible-lint b/scripts/verible-lint
@@ -11,14 +11,14 @@ find $ROOT/ \
     -not \( -path '*.bender/*' -prune \) \
     -not \( -path '*morty/*' -prune \) \
     -not \( -path '*test/*' -prune \) \
-    -not \( -path '*systems/pulpopen/idma_axi_to_mem.sv' -prune \) \
+    -not \( -path '*idma_desc64_reader.sv*' -prune \) \
     -name '*.sv'
 
 find $ROOT/ \
     -not \( -path '*.bender/*' -prune \) \
     -not \( -path '*morty/*' -prune \) \
     -not \( -path '*test/*' -prune \) \
-    -not \( -path '*systems/pulpopen/idma_axi_to_mem.sv' -prune \) \
+    -not \( -path '*idma_desc64_reader.sv*' -prune \) \
     -name '*.sv' \
     | xargs verible-verilog-lint \
     --rules=-interface-name-style --lint_fatal --parse_fatal \

diff --git a/scripts/waves/vsim_fe_desc64.do b/scripts/waves/vsim_fe_desc64.do
@@ -0,0 +1,17 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -position end i_dut/clk_i
+add wave -position end i_dut/rst_ni
+add wave -position end i_dut/master_req_o
+add wave -position end i_dut/master_rsp_i
+add wave -position end i_dut/slave_req_i
+add wave -position end i_dut/slave_rsp_o
+add wave -position end i_dut/idma_req_o
+add wave -position end i_dut/idma_req_ready_i
+add wave -position end i_dut/idma_req_valid_o
+add wave -position end i_dut/idma_rsp_ready_o
+add wave -position end i_dut/idma_rsp_valid_i
+add wave -position end i_dut/idma_busy_i
+add wave -position end i_dut/irq_o
+
+quietly wave cursor active 1