[WIP] change inst64_snitch_pkg bender target to only rtl

pulp-platform · da-gazzi · Jun 20, 2024 · Jun 21, 2024 · Jun 21, 2024 · Jun 21, 2024
commit 3d018f067a7e0c2c7293cd972d1d361efe1a6d8a
diff --git a/Bender.yml b/Bender.yml
@@ -68,7 +68,7 @@ sources:
       - src/midend/idma_rt_midend.sv
 
   # RISC-V opcode package for ooc use of inst64
-  - target: all(rtl,snitch_cluster)
+  - target: rtl
     files:
       # Level 0
       - src/frontend/inst64/idma_inst64_snitch_pkg.sv

diff --git a/src/pulp_idma_wrap.sv b/src/pulp_idma_wrap.sv
  parameter  int unsigned BE_WIDTH               = DATA_WIDTH / 8,
  parameter  type         axi_req_t              = logic,
  parameter  type         axi_resp_t             = logic,
  // bidirectional streams: range 1 to 8                   
  parameter  int unsigned NUM_BIDIR_STREAMS      = 1,
  parameter  int unsigned NB_OUTSND_BURSTS       = 8,
  // queue depth per stream                   
  parameter  int unsigned GLOBAL_QUEUE_DEPTH     = 2,
  // mux read ports between tcdm-tcdm and tcdm-axi?                 
  parameter  bit          MUX_READ               = 1'b0,
  // 4 ports per stream if read ports muxed, otherwise 6
  localparam int unsigned NB_TCDM_PORTS_PER_STRM = 4 + (~MUX_READ) * 2
 ) (  // verilog_format: off // verible does not manage to align this :(
  input logic                    clk_i,
  input logic                    rst_ni,
  input logic                    test_mode_i,
                                 XBAR_PERIPH_BUS.Slave pe_ctrl_slave[NB_PE_PORTS-1:0],
                                 XBAR_TCDM_BUS.Slave ctrl_slave[NB_CORES-1:0],
                                 hci_core_intf.master tcdm_master[NB_TCDM_PORTS_PER_STRM*NUM_BIDIR_STREAMS-1:0],
  output                         axi_req_t [NUM_BIDIR_STREAMS-1:0] ext_master_req_o,
  input                          axi_resp_t [NUM_BIDIR_STREAMS-1:0] ext_master_rsp_i,
  output logic [NB_CORES-1:0]    term_event_o,
  output logic [NB_PE_PORTS-1:0] term_event_pe_o,
  output logic [NB_PE_PORTS-1:0] term_irq_pe_o,
  output logic                   busy_o
 ); // verilog_format: on 

  localparam int unsigned NumRegs = NB_CORES + NB_PE_PORTS;
  localparam int unsigned NumStreams = 32'd2 * NUM_BIDIR_STREAMS;
    if (s[0] == 1'b0) begin : gen_cpy_out

      // Meta Channel Widths
      localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(
          AXI_ADDR_WIDTH, AXI_ID_WIDTH, AXI_USER_WIDTH
      );
      localparam int unsigned init_req_chan_width = $bits(init_req_chan_t);
      localparam int unsigned obi_a_chan_width = $bits(obi_a_chan_t);

      function int unsigned max_width(input int unsigned a, b);
        return (a > b) ? a : b;
      endfunction

    end else begin : gen_cpy_in

      // Meta Channel Widths
      localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(
          AXI_ADDR_WIDTH, AXI_ID_WIDTH, AXI_USER_WIDTH
      );
      localparam int unsigned init_req_chan_width = $bits(init_req_chan_t);
      localparam int unsigned obi_a_chan_width = $bits(obi_a_chan_t);

      function int unsigned max_width(input int unsigned a, b);
        return (a > b) ? a : b;
      endfunction

  // ------------------------------------------------------
  // MUX read OBI connections if specified
  // ------------------------------------------------------
  for (genvar s = 0; s < NUM_BIDIR_STREAMS; s++) begin
    if (MUX_READ) begin
      obi_pkg::obi_cfg_t sbr_obi_cfg;
      assign sbr_obi_cfg = obi_pkg::obi_default_cfg(
          AXI_ADDR_WIDTH, AXI_DATA_WIDTH, 0, obi_pkg::ObiMinimalOptionalConfig
        .mgr_port_req_o (obi_read_req_muxed),
        .mgr_port_rsp_i (obi_read_rsp_to_mux)
      );
    end else begin  // if (MUX_READ)
      // pass through the read req/rsp from/to dma
      assign obi_read_req_muxed  = obi_read_req_from_dma;
      assign obi_read_rsp_to_dma = obi_read_rsp_to_mux;
  // ------------------------------------------------------
  // TCDM connections
  // ------------------------------------------------------
  for (genvar s = 0; s < NUM_BIDIR_STREAMS; s++) begin

    logic tcdm_master_we_0;
    logic tcdm_master_we_1;
    assign tcdm_master[NB_TCDM_PORTS_PER_STRM*s+2].wen   = !tcdm_master_we_2;
    assign tcdm_master[NB_TCDM_PORTS_PER_STRM*s+3].wen   = !tcdm_master_we_3;

    if (!MUX_READ) begin // if we don't mux the read, we have 6*NUM_BIDIR_STREAMS interfaces and the reorg
                         // interface goes straight to TCDM masters 5 and 4. 
      mem_to_banks #(
        .AddrWidth(AXI_ADDR_WIDTH),
        .DataWidth(AXI_DATA_WIDTH),
	parameter int unsigned BE_WIDTH = DATA_WIDTH / 8,
	parameter type axi_req_t = logic,
	parameter type axi_resp_t = logic,
	// bidirectional streams: range 1 to 8
Check warning on line 33 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L33 `Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]` Raw output `message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:33 column:41}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:33 column:41} end:{line:36}} text:" // bidirectional streams: range 1 to 8\n // queue depth per stream\n // mux read ports between tcdm-tcdm and tcdm-axi?\n"}`
	parameter int unsigned NUM_BIDIR_STREAMS = 1,
	parameter int unsigned NB_OUTSND_BURSTS = 8,
	// queue depth per stream
Check warning on line 36 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L36 `Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]` Raw output `message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:36 column:28}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	parameter int unsigned GLOBAL_QUEUE_DEPTH = 2,
	// mux read ports between tcdm-tcdm and tcdm-axi?
Check warning on line 38 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L38 `Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]` Raw output `message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:38 column:52}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	parameter bit MUX_READ = 1'b0,
	// 4 ports per stream if read ports muxed, otherwise 6
	localparam int unsigned NB_TCDM_PORTS_PER_STRM = 4 + (~MUX_READ) * 2
Check warning on line 41 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L41 `Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]` Raw output `message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:41 column:27}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	) ( // verilog_format: off // verible does not manage to align this :(
	input logic clk_i,
	input logic rst_ni,
	input logic test_mode_i,
	XBAR_PERIPH_BUS.Slave pe_ctrl_slave[NB_PE_PORTS-1:0],
Check warning on line 46 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L46 `Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]` Raw output `message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:46 column:70}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	XBAR_TCDM_BUS.Slave ctrl_slave[NB_CORES-1:0],
Check warning on line 47 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L47 `Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]` Raw output `message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:47 column:65}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	hci_core_intf.master tcdm_master[NB_TCDM_PORTS_PER_STRM*NUM_BIDIR_STREAMS-1:0],
Check warning on line 48 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L48 `Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]` Raw output `message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:48 column:67}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}` Check warning on line 48 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L48 `Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]` Raw output `message:"Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:48 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	output axi_req_t [NUM_BIDIR_STREAMS-1:0] ext_master_req_o,
	input axi_resp_t [NUM_BIDIR_STREAMS-1:0] ext_master_rsp_i,
	output logic [NB_CORES-1:0] term_event_o,
	output logic [NB_PE_PORTS-1:0] term_event_pe_o,
	output logic [NB_PE_PORTS-1:0] term_irq_pe_o,
	output logic busy_o
	); // verilog_format: on
Check warning on line 56 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L56 `Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]` Raw output `message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:56 column:25}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:56 column:25} end:{line:57}} text:"); // verilog_format: on\n"}`

	localparam int unsigned NumRegs = NB_CORES + NB_PE_PORTS;
	localparam int unsigned NumStreams = 32'd2 * NUM_BIDIR_STREAMS;
	if (s[0] == 1'b0) begin : gen_cpy_out

	// Meta Channel Widths
	localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(
Check warning on line 360 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L360 `Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]` Raw output `message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:360 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	AXI_ADDR_WIDTH, AXI_ID_WIDTH, AXI_USER_WIDTH
	);
	localparam int unsigned init_req_chan_width = $bits(init_req_chan_t);
Check warning on line 363 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L363 `Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]` Raw output `message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:363 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	localparam int unsigned obi_a_chan_width = $bits(obi_a_chan_t);
Check warning on line 364 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L364 `Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]` Raw output `message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:364 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`

	function int unsigned max_width(input int unsigned a, b);
Check warning on line 366 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L366 `Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]` Raw output `message:"Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:366 column:29}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}` Check warning on line 366 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L366 `Explicitly define a storage type for every function parameter. [Style: function-task-argument-types] [explicit-function-task-parameter-type]` Raw output `message:"Explicitly define a storage type for every function parameter. [Style: function-task-argument-types] [explicit-function-task-parameter-type]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:366 column:61}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	return (a > b) ? a : b;
	endfunction

	end else begin : gen_cpy_in

	// Meta Channel Widths
	localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(
Check warning on line 469 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L469 `Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]` Raw output `message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:469 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	AXI_ADDR_WIDTH, AXI_ID_WIDTH, AXI_USER_WIDTH
	);
	localparam int unsigned init_req_chan_width = $bits(init_req_chan_t);
Check warning on line 472 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L472 `Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]` Raw output `message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:472 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	localparam int unsigned obi_a_chan_width = $bits(obi_a_chan_t);
Check warning on line 473 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L473 `Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]` Raw output `message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:473 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`

	function int unsigned max_width(input int unsigned a, b);
Check warning on line 475 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L475 `Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]` Raw output `message:"Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:475 column:29}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}` Check warning on line 475 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L475 `Explicitly define a storage type for every function parameter. [Style: function-task-argument-types] [explicit-function-task-parameter-type]` Raw output `message:"Explicitly define a storage type for every function parameter. [Style: function-task-argument-types] [explicit-function-task-parameter-type]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:475 column:61}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	return (a > b) ? a : b;
	endfunction

	// ------------------------------------------------------
	// MUX read OBI connections if specified
	// ------------------------------------------------------
	for (genvar s = 0; s < NUM_BIDIR_STREAMS; s++) begin
Check warning on line 593 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L593 `All generate block statements must have a label [Style: generate-statements] [generate-label]` Raw output `message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:593 column:50}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	if (MUX_READ) begin
Check warning on line 594 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L594 `All generate block statements must have a label [Style: generate-statements] [generate-label]` Raw output `message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:594 column:19}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	obi_pkg::obi_cfg_t sbr_obi_cfg;
	assign sbr_obi_cfg = obi_pkg::obi_default_cfg(
	AXI_ADDR_WIDTH, AXI_DATA_WIDTH, 0, obi_pkg::ObiMinimalOptionalConfig
	.mgr_port_req_o (obi_read_req_muxed),
	.mgr_port_rsp_i (obi_read_rsp_to_mux)
	);
	end else begin // if (MUX_READ)
Check warning on line 621 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L621 `All generate block statements must have a label [Style: generate-statements] [generate-label]` Raw output `message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:621 column:14}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	// pass through the read req/rsp from/to dma
	assign obi_read_req_muxed = obi_read_req_from_dma;
	assign obi_read_rsp_to_dma = obi_read_rsp_to_mux;
	// ------------------------------------------------------
	// TCDM connections
	// ------------------------------------------------------
	for (genvar s = 0; s < NUM_BIDIR_STREAMS; s++) begin
Check warning on line 632 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L632 `All generate block statements must have a label [Style: generate-statements] [generate-label]` Raw output `message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:632 column:50}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`

	logic tcdm_master_we_0;
	logic tcdm_master_we_1;
	assign tcdm_master[NB_TCDM_PORTS_PER_STRM*s+2].wen = !tcdm_master_we_2;
	assign tcdm_master[NB_TCDM_PORTS_PER_STRM*s+3].wen = !tcdm_master_we_3;

	if (!MUX_READ) begin // if we don't mux the read, we have 6*NUM_BIDIR_STREAMS interfaces and the reorg
Check warning on line 697 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L697 `All generate block statements must have a label [Style: generate-statements] [generate-label]` Raw output `message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:697 column:20}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}` Check warning on line 697 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L697 `Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]` Raw output `message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:697 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}`
	// interface goes straight to TCDM masters 5 and 4.
Check warning on line 698 in src/pulp_idma_wrap.sv GitHub Actions / verible-verilog-lint [verible-verilog-lint] src/pulp_idma_wrap.sv#L698 `Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]` Raw output `message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"src/pulp_idma_wrap.sv" range:{start:{line:698 column:77}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:698 column:77} end:{line:699}} text:" // interface goes straight to TCDM masters 5 and 4.\n"}`
	mem_to_banks #(
	.AddrWidth(AXI_ADDR_WIDTH),
	.DataWidth(AXI_DATA_WIDTH),