merge ConfigurationError and RegisterMapError (#42, rggen/rggen#237)

spec/rggen/vhdl/global/library_name_spec.rb

@@ -51,7 +51,7 @@
 
   describe 'エラーチェック' do
     context 'ライブラリ名が入力パターンに一致しない場合' do
-      it 'ConfigurationErrorを起こす' do
+      it 'SourceErrorを起こす' do
         [
           '_',
           random_string(/_\w+/),
@@ -61,7 +61,7 @@
           random_string(/[a-z_]\s+[a-z_]/i)
         ].each do |invalid_name|
           expect { create_configuration(library_name: invalid_name) }
-            .to raise_configuration_error("illegal input value for library name: #{invalid_name.inspect}")
+            .to raise_source_error("illegal input value for library name: #{invalid_name.inspect}")
         end
       end
     end

spec/rggen/vhdl/register_map/name_spec.rb

@@ -38,26 +38,26 @@ def random_updown_case(keyword)
   end
 
   context 'レジスタブロック名がVHDLの予約語に一致する場合' do
-    it 'RegiterMapErrorを起こす' do
+    it 'SourceErrorを起こす' do
       vhdl_keywords.each do |keyword|
         expect {
           create_register_map do
             register_block { name keyword }
           end
-        }.to raise_register_map_error "vhdl keyword is not allowed for register block name: #{keyword}"
+        }.to raise_source_error "vhdl keyword is not allowed for register block name: #{keyword}"
 
         kw = random_updown_case(keyword)
         expect {
           create_register_map do
             register_block { name kw }
           end
-        }.to raise_register_map_error "vhdl keyword is not allowed for register block name: #{keyword}"
+        }.to raise_source_error "vhdl keyword is not allowed for register block name: #{keyword}"
       end
     end
   end
 
   context 'レジスタファイル名がVHDLの予約語に一致する場合' do
-    it 'RegiterMapErrorを起こす' do
+    it 'SourceErrorを起こす' do
       vhdl_keywords.each do |keyword|
         expect {
           create_register_map do
@@ -66,7 +66,7 @@ def random_updown_case(keyword)
               register_file { name keyword }
             end
           end
-        }.to raise_register_map_error "vhdl keyword is not allowed for register file name: #{keyword}"
+        }.to raise_source_error "vhdl keyword is not allowed for register file name: #{keyword}"
 
         kw = random_updown_case(keyword)
         expect {
@@ -76,13 +76,13 @@ def random_updown_case(keyword)
               register_file { name kw }
             end
           end
-        }.to raise_register_map_error "vhdl keyword is not allowed for register file name: #{keyword}"
+        }.to raise_source_error "vhdl keyword is not allowed for register file name: #{keyword}"
       end
     end
   end
 
   context 'レジスタ名がVHDLの予約語に一致する場合' do
-    it 'RegiterMapErrorを起こす' do
+    it 'SourceErrorを起こす' do
       vhdl_keywords.each do |keyword|
         expect {
           create_register_map do
@@ -91,7 +91,7 @@ def random_updown_case(keyword)
               register { name keyword }
             end
           end
-        }.to raise_register_map_error "vhdl keyword is not allowed for register name: #{keyword}"
+        }.to raise_source_error "vhdl keyword is not allowed for register name: #{keyword}"
 
         kw = random_updown_case(keyword)
         expect {
@@ -101,13 +101,13 @@ def random_updown_case(keyword)
               register { name kw }
             end
           end
-        }.to raise_register_map_error "vhdl keyword is not allowed for register name: #{keyword}"
+        }.to raise_source_error "vhdl keyword is not allowed for register name: #{keyword}"
       end
     end
   end
 
   context 'ビットフィールド名がVHDLの予約語に一致する場合' do
-    it 'RegiterMapErrorを起こす' do
+    it 'SourceErrorを起こす' do
       vhdl_keywords.each do |keyword|
         expect {
           create_register_map do
@@ -119,7 +119,7 @@ def random_updown_case(keyword)
               end
             end
           end
-        }.to raise_register_map_error "vhdl keyword is not allowed for bit field name: #{keyword}"
+        }.to raise_source_error "vhdl keyword is not allowed for bit field name: #{keyword}"
 
         kw = random_updown_case(keyword)
         expect {
@@ -132,7 +132,7 @@ def random_updown_case(keyword)
               end
             end
           end
-        }.to raise_register_map_error "vhdl keyword is not allowed for bit field name: #{keyword}"
+        }.to raise_source_error "vhdl keyword is not allowed for bit field name: #{keyword}"
       end
     end
   end