addr srmcfg CSR tests

riscv-non-isa · Dec 30, 2023 · 93d73cf · 93d73cf
1 parent 0feb005
commit 93d73cf
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Showing 2 changed files with 7 additions and 6 deletions.
diff --git a/riscv-test-suite/rv32i_m/Ssqosid/src/srmcfg_mstateen0.S b/riscv-test-suite/rv32i_m/Ssqosid/src/srmcfg_mstateen0.S
@@ -19,7 +19,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-  RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zicsr.*Smstateen.*Ssqosid.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", srmcfg_mstateen)
+  RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zicsr.*Smstateen.*Ssqosid.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True", srmcfg_mstateen)
 
   RVTEST_SIGBASE(x1,signature_x1)
 
@@ -39,6 +39,7 @@ no_TOR_try_NAPOT:
   li x2, 0x1FFFFFFF
   csrw pmpaddr0, x2
 Mend_PMP:
+  csrw satp, x0
 
   li x2, 0x05550AAA
   csrw CSR_SRMCFG, x2
@@ -67,12 +68,12 @@ Mend_PMP:
   RVTEST_SIGUPD(x1, x2, 0 * REGWIDTH)
 
   # Enable Smode access to srmcfg
-  csrr x3, CSR_MSTATEEN0
-  li x2, MSTATEEN0_PRIV114
+  csrr x3, CSR_MSTATEEN0H
+  li x2, MSTATEEN0H_PRIV114
   or x3, x2, x2
-  csrw CSR_MSTATEEN0, x3
+  csrw CSR_MSTATEEN0H, x3
 
-  csrr x2, CSR_MSTATEEN0
+  csrr x2, CSR_MSTATEEN0H
   RVTEST_SIGUPD(x1, x2, 1 * REGWIDTH)
 
   # transfer to Smode and access the CSR - access succeeds

diff --git a/riscv-test-suite/rv64i_m/Ssqosid/src/srmcfg_mstateen0.S b/riscv-test-suite/rv64i_m/Ssqosid/src/srmcfg_mstateen0.S
@@ -19,7 +19,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-  RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zicsr.*Smstateen.*Ssqosid.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", srmcfg_mstateen)
+  RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zicsr.*Smstateen.*Ssqosid.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True", srmcfg_mstateen)
 
   RVTEST_SIGBASE(x1,signature_x1)