Add support for Zilsd and Zcmlsd extensions

coverage/dataset.cgf

@@ -171,6 +171,24 @@ datasets:
     x28: 0
     x30: 0
 
+  pair_regs_zilsd: &pair_regs_zilsd
+    x0: 0
+    x2: 0
+    x4: 0
+    x6: 0
+    x8: 0
+    x10: 0
+    x12: 0
+    x14: 0
+    x16: 0
+    x18: 0
+    x20: 0
+    x22: 0
+    x24: 0
+    x26: 0
+    x28: 0
+    x30: 0
+
   c_regs: &c_regs
     x8: 0
     x9: 0
@@ -246,6 +264,28 @@ datasets:
     x30: 0
     x31: 0
 
+  c_pair_regs: &c_pair_regs
+    x8: 0
+    x10: 0
+    x12: 0
+    x14: 0
+
+  c_pair_regs_mx2: &c_pair_regs_mx2
+    x4: 0
+    x6: 0
+    x8: 0
+    x10: 0
+    x12: 0
+    x14: 0
+    x16: 0
+    x18: 0
+    x20: 0
+    x22: 0
+    x24: 0
+    x26: 0
+    x28: 0
+    x30: 0
+
   cbfmt_immval_sgn: &cbfmt_immval_sgn
     'imm_val == (-2**(6-1))': 0
     'imm_val == 0': 0

coverage/zilsd/rv32zilsd.cgf

@@ -0,0 +1,128 @@
+# See License https://gitlab.com/vyoma_systems/common/-/blob/main/LICENSE.BSD3.vyoma for more details
+
+ld:
+    config: 
+      - check ISA:=regex(.*I.*Zilsd.*)
+    opcode: 
+      ldz: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *pair_regs_zilsd
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+        'ea_align == 0 and (imm_val % 8) == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 1': 0
+        'ea_align == 0 and (imm_val % 8) == 2': 0
+        'ea_align == 0 and (imm_val % 8) == 3': 0
+        'ea_align == 0 and (imm_val % 8) == 4': 0
+        'ea_align == 0 and (imm_val % 8) == 5': 0
+        'ea_align == 0 and (imm_val % 8) == 6': 0
+        'ea_align == 0 and (imm_val % 8) == 7': 0
+        'imm_val > 0': 0
+        'imm_val < 0': 0
+        'imm_val == 0': 0       
+
+
+sd:
+    config: 
+      - check ISA:=regex(.*I.*Zilsd.*)
+    opcode: 
+      sdz: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *pair_regs_zilsd
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'ea_align == 0 and (imm_val % 8) == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 1': 0
+        'ea_align == 0 and (imm_val % 8) == 2': 0
+        'ea_align == 0 and (imm_val % 8) == 3': 0
+        'ea_align == 0 and (imm_val % 8) == 4': 0
+        'ea_align == 0 and (imm_val % 8) == 5': 0
+        'ea_align == 0 and (imm_val % 8) == 6': 0
+        'ea_align == 0 and (imm_val % 8) == 7': 0
+        'imm_val > 0': 0
+        'imm_val < 0': 0
+        'imm_val == 0': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]
+
+
+
+cldsp:
+    config: 
+      - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*)
+    opcode: 
+      c.ldspz: 0
+    rd: 
+      <<: *pair_regs
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0
+
+csdsp:
+    config: 
+      - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*)
+    opcode: 
+      c.sdspz: 0
+    rs2: 
+      <<: *pair_regs_zilsd
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0
+
+cld:
+    config: 
+      - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*)
+    opcode: 
+      c.ldz: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_pair_regs
+    op_comb:
+        'rs1 == rd': 0
+        'rs1 != rd': 0
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0
+
+csd:
+    config: 
+      - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*)
+    opcode: 
+      c.sdz: 0
+    rs1: 
+      <<: *c_regs
+    rs2: 
+      <<: *c_pair_regs
+    op_comb:
+        'rs1 != rs2': 0
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        <<: [  *base_rs2val_sgn]
+        abstract_comb:
+          <<: [*rs2val_walking]
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0

coverage/zilsd/rv32zilsd_priv.cgf

@@ -0,0 +1,39 @@
+misalign-sd:
+  config:
+    - check ISA:=regex(.*I.*Zilsd.*); check hw_data_misaligned_support:=True
+    - check ISA:=regex(.*I.*Zicsr.*Zilsd.); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
+  cond: check ISA:=regex(.*32.*I.*Zicsr.*)
+  mnemonics:
+    sdz: 0
+  rs1: 
+    <<: *all_regs_mx0
+  rs2: 
+    <<: *pair_regs_zilsd
+  val_comb:
+    'ea_align == 1': 0
+    'ea_align == 2': 0
+    'ea_align == 3': 0
+    'ea_align == 4': 0
+    'ea_align == 5': 0
+    'ea_align == 6': 0
+    'ea_align == 7': 0
+
+misalign-ld:
+  config:
+    - check ISA:=regex(.*I.*Zilsd.*); check hw_data_misaligned_support:=True
+    - check ISA:=regex(.*I.*Zicsr.*Zilsd.); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
+  cond: check ISA:=regex(.*32.*I.*Zicsr.*)
+  mnemonics:
+    ldz: 0
+  rs1: 
+    <<: *all_regs_mx0
+  rd: 
+    <<: *pair_regs_zilsd
+  val_comb:
+    'ea_align == 1': 0
+    'ea_align == 2': 0
+    'ea_align == 3': 0
+    'ea_align == 4': 0
+    'ea_align == 5': 0
+    'ea_align == 6': 0
+    'ea_align == 7': 0

riscof-plugins/rv32/sail_cSim/env/model_test.h

@@ -1,6 +1,10 @@
 #ifndef _COMPLIANCE_MODEL_H
 #define _COMPLIANCE_MODEL_H
-
+#if XLEN == 64
+  #define ALIGNMENT 4
+#else
+  #define ALIGNMENT 2
+#endif
 #define RVMODEL_DATA_SECTION \
         .pushsection .tohost,"aw",@progbits;                            \
         .align 8; .global tohost; tohost: .dword 0;                     \
@@ -23,7 +27,7 @@ li x1, 1                ;\
 //RV_COMPLIANCE_DATA_BEGIN                                                                          
 #define RVMODEL_DATA_BEGIN		;\
 RVMODEL_DATA_SECTION			;\
-.align 4                  ;\
+.align ALIGNMENT;\
 .global begin_signature   ;\
 begin_signature:
 

riscof-plugins/rv32/sail_cSim/riscof_sail_cSim.py

@@ -88,6 +88,11 @@ def build(self, isa_yaml, platform_yaml):
             self.isa += 'f'
         if "D" in ispec["ISA"]:
             self.isa += 'd'
+        if "Zilsd" in ispec["ISA"]:
+            self.isa += 'Zilsd'
+            self.zilsdflg = True
+        if "Zclsd" in ispec["ISA"]:
+            self.isa += '_Zclsd'
         objdump = "riscv{0}-unknown-elf-objdump".format(self.xlen)
         if not self.docker:
             if shutil.which(objdump) is None:
@@ -133,9 +138,13 @@ def runTests(self, testList, cgf_file=None, header_file= None):
 
             execute += self.objdump_cmd.format(elf, self.xlen, 'ref.disass')
             sig_file = os.path.join(test_dir, self.name[:-1] + ".signature")
-
-            execute += self.sail_exe[self.xlen] + '  -i -v --trace=step  --pmp-count=16 --pmp-grain=0  --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
-
+            cmd = ''
+            if "Zilsd" in self.isa:
+                cmd = cmd + ' --enable-zilsd'  
+            if "Zclsd" in self.isa:
+                cmd = cmd + ' --enable-zclsd'
+            execute += self.sail_exe[self.xlen] + cmd + '  -i -v --trace=step  --pmp-count=16 --pmp-grain=0  --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
+            execute +=  f'perl -pi -e \'s/^\[/\\n\\n\[/\' {test_name}.log;'
             cov_str = ' '
             for label in testentry['coverage_labels']:
                 cov_str+=' -l '+label
@@ -153,8 +162,8 @@ def runTests(self, testList, cgf_file=None, header_file= None):
                         -t {0}.log --parser-name c_sail -o coverage.rpt  \
                         --sig-label begin_signature  end_signature \
                         --test-label rvtest_code_begin rvtest_code_end \
-                        -e ref.elf -c {1} -x{2} {3} {4} {5};'.format(\
-                        test_name, ' -c '.join(cgf_file), self.xlen, cov_str, header_file_flag, cgf_mac)
+                        -e ref.elf -c {1} --zilsdFlg {6} -x{2} {3} {4} {5};'.format(\
+                        test_name, ' -c '.join(cgf_file), self.xlen, cov_str, header_file_flag, cgf_mac,self.zilsdflg)
             else:
                 coverage_cmd = ''
 

riscof-plugins/rv32/spike_simple/riscof_spike_simple.py

@@ -104,6 +104,11 @@ def build(self, isa_yaml, platform_yaml):
           self.isa += 'd'
       if "C" in ispec["ISA"]:
           self.isa += 'c'
+      if "Zilsd" in ispec["ISA"]:
+          self.isa += 'Zilsd'
+        #   self.zilsdflg = True
+      if "Zclsd" in ispec["ISA"]:
+          self.isa += '_Zclsd'
 
       #TODO: The following assumes you are using the riscv-gcc toolchain. If
       #      not please change appropriately

riscv-ctg/riscv_ctg/constants.py

@@ -191,7 +191,7 @@ def gen_bitmanip_dataset(bit_width,sign=True):
 # increment each value in dataset, increment each value in dataset, add them to the dataset
     return dataset + [x - 1 for x in dataset] + [x+1 for x in dataset] + dataset0
 
-template_fnames = ["template.yaml","imc.yaml","fd.yaml","inx.yaml"]
+template_fnames = ["template.yaml","imc.yaml","fd.yaml","inx.yaml","zilsd.yaml"]
 
 template_files = [os.path.join(root,"data/"+f) for f in template_fnames]
 

riscv-ctg/riscv_ctg/data/template.yaml

@@ -6,7 +6,10 @@ metadata:
   c_regs: &c_regs "['x'+str(x) for x in range(8,16)]"
   pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
   rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]"
-
+  pair_regs_zclsd: &pair_regs_zclsd "['x'+str(x) for x in range(2,31 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
+  pair_regs_zilsd: &pair_regs_zilsd "['x'+str(x) for x in range(0,31 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
+  c_pair_regs: &c_pair_regs "['x'+str(x) for x in range(8,16,2)]"
+
 aes32dsi:
   sig:
     stride: 1