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pmu updates #165

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pmu updates #165

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atishp04
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This series adds one new function and provides few more improvements
and clarification to existing function/events.

The event discovery is improved from last RFC patch by Samuel[1].
While the first version required 2 SBI calls for hardware and cache
events respectively, this version requires only 1 call. Apart from
that it also supports raw/firmware events in case we need that in
the future.

[1]:https://lists.riscv.org/g/tech-prs/message/964

# Describe the purpose of this series. The information you put here
# will be used by the project maintainer to make a decision whether
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# very detailed and link to any relevant discussions or sites that the
# maintainer can review to better understand your proposed changes. If you
# only have a single patch in your series, the contents of the cover
# letter will be appended to the "under-the-cut" portion of the patch.

# Lines starting with # will be removed from the cover letter. You can
# use them to add notes or reminders to yourself. If you want to use
# markdown headers in your cover letter, start the line with ">#".

# You can add trailers to the cover letter. Any email addresses found in
# these trailers will be added to the addresses specified/generated
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To: [email protected]

Signed-off-by: Atish Patra <[email protected]>

---
Changes in v2:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v1: https://lore.kernel.org/r/[email protected]



--- b4-submit-tracking ---
# This section is used internally by b4 prep for tracking purposes.
{
  "series": {
    "revision": 2,
    "change-id": "20240910-pmu_updates-f6c34f2a7e3c",
    "prefixes": [],
    "history": {
      "v1": [
        "[email protected]"
      ]
    }
  }
}
The priv v1.13 specification only defines 6 bits for mhpmeventX while allowing
implementation to freely choose lower 58 bits.
To maintain backward compatibility add a new raw event type(riscv-non-isa#3) that allows
SBI implementation to update mhpmeventX with 58 bits instead of 48 bits
defined for raw event type (riscv-non-isa#2).

Closes: riscv/riscv-isa-manual#1578

Signed-off-by: Atish Patra <[email protected]>
The supervisor software may need to be aware of which standard or
raw events are allowed by the platform. This will help the supervisor
software to advertise only those events instead of all standard events.
In addition to that, it may just waste time trying to match a counter
for each invalid event at runtime which may lead to undesirable results.
Currently, this problem is solved by invoking CFG_MATCH call for each
event which is not ideal as it may increase the bootime with unnecessary
SBI calls at boot time.

Introduce a new function that allows to discover support events with a
single SBI call which is very efficient.

Signed-off-by: Atish Patra <[email protected]>
…ons.

The counter start and stop function has multiple flags but the the error
table doesn't specify that the implementation must return invalid parameter
error if an undefined bit is set in the given flag parameter.

Closes: riscv-non-isa#145

Signed-off-by: Atish Patra <[email protected]>
[cols="1,2,7", width=90%, align="center", options="header"]
|===
| Word | Name | Encoding
| 0 | event_idx | BIT[0-19] - Describes `event_idx`
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Suggest changing "BIT[0-19]" to "BIT[0:19]", using the same bit format representation as other sections.
The same applies to the reset of BIT[] below.

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Done. PTAL.

this field if valid `event_idx` and `event_data`
(if applicable) specified in this entry.
BIT[1-31] - Reserved for future purpose. Must be zero.
| 2-3 | event_data | BIT[0-63] - Valid only if `event_idx.type` is either
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Currently, the SBI spec doesn't have tables for event types. It is more user friendly to have a table without the user having to scroll through the whole chapter to find the event type # value and its meaning. Then we can add a cross-reference link here as well .

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Done. PTAL.

@atishp04
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Closing the PR as it was just intended to trigger the CI.

@atishp04 atishp04 closed this Sep 16, 2024
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