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add extra information into exception reporting #373

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merged 17 commits into from
Sep 23, 2024
Merged

add extra information into exception reporting #373

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e1a458a
add extra information into exception reoprting
tariqkurd-repo Sep 19, 2024
99e7c82
clarify that stval fields match mtval for cheri faults
tariqkurd-repo Sep 19, 2024
e5c2864
clarify mtval2 address
tariqkurd-repo Sep 19, 2024
1ff37d1
add vstval2
tariqkurd-repo Sep 19, 2024
a3550a7
add missing file
tariqkurd-repo Sep 20, 2024
e43c090
move vstval2 to hypervisor section
tariqkurd-repo Sep 20, 2024
acea223
clarify it's the effective address
tariqkurd-repo Sep 20, 2024
9dc0424
Add vstval and remove cap_idx from Xtval2
tariqkurd-repo Sep 20, 2024
31e1376
add new file
tariqkurd-repo Sep 20, 2024
332b2bc
Update src/riscv-integration.adoc
tariqkurd-repo Sep 23, 2024
db7239f
Update src/hypervisor-integration.adoc
tariqkurd-repo Sep 23, 2024
7e3f642
Update src/hypervisor-integration.adoc
tariqkurd-repo Sep 23, 2024
50d46f5
Update src/riscv-integration.adoc
tariqkurd-repo Sep 23, 2024
d816c67
remove comments
tariqkurd-repo Sep 23, 2024
ee7b991
Update src/hypervisor-integration.adoc
tariqkurd-repo Sep 23, 2024
e2fec8b
Update src/riscv-integration.adoc
tariqkurd-repo Sep 23, 2024
ac69a96
clarify that Xtval2 regs are all updated the same way for all cheri e…
tariqkurd-repo Sep 23, 2024
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4 changes: 2 additions & 2 deletions src/img/stval2reg.edn
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Expand Up @@ -6,9 +6,9 @@
(def left-margin 100)
(def right-margin 100)
(def boxes-per-row 32)
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1"])})
(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "SXLEN-1"])})

(draw-box "Addr" {:span 32})

(draw-box "MXLEN" {:span 32 :borders {}})
(draw-box "SXLEN" {:span 32 :borders {}})
----
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24 changes: 23 additions & 1 deletion src/riscv-integration.adoc
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Expand Up @@ -819,6 +819,8 @@ authorising capability which caused the exception.

<<mtval2>> is set to zero for all PCC faults, and follows the standard rules for non-CHERI exceptions.
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If <<mtval>> is read-only-zero then <<mtval2>> is also read-only-zero.

.Machine trap value register 2
[#mtval2-format]
include::img/mtval2reg.edn[]
Expand Down Expand Up @@ -1032,17 +1034,37 @@ The fields are identical to <<mtval>> for CHERI exceptions.

The <<stval2>> register is an SXLEN-bit read-write register.

The CSR address is 0x14b.
The CSR address is 0x24b.

When a fault is taken into S-mode <<stval2>> is updated as for <<mtval2>> for all CHERI memory access traps.
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It is set to zero in all other cases.

NOTE: This is not a standard RISC-V CSR, but <<mtval2>> is. 0x14b is the regular location for the CSR.

<<stval2>> holds the same set of values that <<mtval2>> can hold.

.Supervisor trap value register 2
[#stval2-format]
include::img/stval2reg.edn[]

[#vstval2,reftext="vstval2"]
==== Virtual Supervisor Trap Value Register 2 (vstval2)
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The <<vstval2>> register is an SXLEN-bit read-write register.

The CSR address is 0x24b.

When a fault is taken into VS-mode <<vstval2>> is updated as for <<mtval2>> for all CHERI memory access traps.
It is set to zero in all other cases.

NOTE: This is not a standard RISC-V CSR, but <<mtval2>> is. 0x24b is the regular location for the CSR.

<<vstval2>> holds the same set of values that <<stval2>> can hold.

.Virtual supervisor trap value register 2
[#vstval2-format]
include::img/vstval2reg.edn[]
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=== Unprivileged CSRs

Unlike machine and supervisor level CSRs, {cheri_base_ext_name} does not require
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