Add simulation

ru551n · Jun 16, 2024 · 9a10bc5 · 9a10bc5
1 parent a95bbb5
commit 9a10bc5
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/run.py b/run.py
@@ -36,9 +36,9 @@ def main():
     args = cli.parse_args()
 
     modules = get_modules(modules_folder=REPO_ROOT / "modules")
-    modules += get_modules(modules_folder=REPO_ROOT / "hdl-module" / "modules")
-
-    simulation_project = SimulationProject(args=args)
+    modules += get_modules(modules_folder=REPO_ROOT / "hdl-modules" / "modules")
+    
+    simulation_project = SimulationProject(args=args, enable_preprocessing=True)
     simulation_project.add_modules(args=args, modules=modules)
 
     if not args.vivado_skip:
@@ -47,7 +47,7 @@ def main():
     create_vhdl_ls_configuration(
         output_path=REPO_ROOT,
         temp_files_path=REPO_ROOT / "out",
-        modules=modules + modules_no_sim,
+        modules=modules,
     )
 
     simulation_project.vunit_proj.main()