✨ add memory coherency logic

[stnolting]

This PR introduces a cleaner memory synchronization (or "ordering" or "coherence") concept for the RISC-V fence isntructions. I am still not completely sure if they are implemented the right way... However, now these instructions will stall the processor until the according synchronization is accomplished:

• fence (load/store fence): flush and reload the CPU's data cache; after that flush and reload the external bus cache
• fence.i (instruction-fetch fence): behave like a fence but will also invalidate the CPU's instruction cache and resets the CPU's instruction fetch front-end

🐛 I've reworked the generic cache module as I had some issues with it when trying to move large data to an external DDR memory via the on-chip debugger.

⚠️ This PR reworks the processor-internal bus system. debug is now an in-band signals that corresponds to the current bus transfer. Furthermore, the sleep signal is removed from the bus.

⚠️ This PR also removes the "halt in sleep-mode" and "halt in debug-mode" features from the watchdog timer. I think without these features the watchdog is more "robust" (or even more secure).