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✨ add memory coherency logic#1176

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stnolting merged 21 commits intomainstnolting/neorv32:mainfrom memory_synchronizationstnolting/neorv32:memory_synchronizationCopy head branch name to clipboardFeb 4, 2025

+653-1,047

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Commits on Feb 1, 2025

• [bus] remove bus mux lock

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Commits on Feb 2, 2025

• Merge branch 'main' into memory_synchronization

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• [bus interface] cleanup signals

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• ⚠️ [wdt] remove "halt if sleep or debug"

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• [rtl] minor cleanups

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• [bus_interface] cleanups

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• [sw/example] update WDT demo

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• [cpu] rework memory fencing/ordering

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• [processor_check] add fence(.i) test case

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• 🐛 [rtl] rework cache module

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• [top] add coherence signals

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• [changelog] add v1.11.0.7

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• [docs] fix bus interface figure

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Commits on Feb 3, 2025

• [docs] minor layout fixes

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• [docs] update cache sections

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• [docs] on-chip debugger always bypass the caches

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• [docs] update fence instruction description

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• Merge branch 'main' into memory_synchronization

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• [rtl] cleanups

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• [package] update version ID

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• [docs] update section "memory coherence"

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