SoundWire: start adding BPT/BRA support #5266

bardliao · 2024-12-06T02:08:37Z

This is a rebase version of #4679
I removed the removal of select' statements at a higher level. in the SND_SOC_SOF_HDA_LINK_BASELINE config in af779a3 which I think it is removed by accident.

drivers/soundwire/stream.c

drivers/soundwire/cadence_master.c

drivers/soundwire/intel_ace2x.c

sound/soc/sof/intel/hda-sdw-bpt.c

drivers/soundwire/intel.h

sound/soc/sof/intel/hda-sdw-bpt.c

plbossart

nice update @bardliao, keep up the good work.

Don't forget to add your own Signed-off-by tag.

plbossart · 2025-01-07T19:31:16Z

Documentation/driver-api/soundwire/summary.rst

-
-
- (2) Multiple data lane support.
+ (1) Multiple data lane support.


didn't you provide multi-lane support already?

Indeed, that is great.

plbossart · 2025-01-07T19:33:48Z

drivers/soundwire/cadence_master.c

@@ -1923,13 +1924,20 @@ void sdw_cdns_config_stream(struct sdw_cdns *cdns,

 		if (cdns->bus.params.m_data_mode != SDW_PORT_DATA_MODE_NORMAL)
 			val |= CDNS_PORTCTRL_TEST_FAILED;
+	} else if (pdi->num == 0) {
+		val |= CDNS_PORTCTRL_BULK_ENABLE;


double-check if this is correct, I wonder if pdi->num == 1 should also be dedicated to BULK.

Yes, changed to if (pdi->num == 0 || pdi->num == 1)

plbossart · 2025-01-07T19:34:08Z

drivers/soundwire/cadence_master.c

+	if (pdi->num == 1)
+		val = 0;
+	else
+		val = pdi->num;


see here PDI1 is used for bulk!

plbossart · 2025-01-07T19:35:36Z

drivers/soundwire/cadence_master.c

 		     val);

-	val = pdi->num;
+	/* The DataPort0 needs to be mapped to both PDI and PDI1 ! */


typo: PDI0 and PDI1.

plbossart · 2025-01-07T19:36:30Z

drivers/soundwire/cadence_master.c

@@ -184,6 +184,7 @@ MODULE_PARM_DESC(cdns_mcp_int_mask, "Cadence MCP IntMask");
 #define CDNS_PORTCTRL_TEST_FAILED		BIT(1)
 #define CDNS_PORTCTRL_DIRN			BIT(7)
 #define CDNS_PORTCTRL_BANK_INVERT		BIT(8)
+#define CDNS_PORTCTRL_BULK_ENABLE		BIT(16)


typo in commit message:
PDI0 taking care of the TX direction and PDI1 of the RX
direction.

plbossart · 2025-01-07T19:40:50Z

sound/soc/sof/intel/hda-sdw-bpt.c

+// This file is provided under a dual BSD/GPLv2 license.  When using or
+// redistributing this file, you may do so under either license.
+//
+// Copyright(c) 2024 Intel Corporation. All rights reserved.


plbossart · 2025-01-07T19:42:44Z

sound/soc/sof/intel/hda-sdw-bpt.c

+#include "../sof-priv.h"
+#include "hda.h"
+
+#define BPT_FREQUENCY		192000


need explanation of this value, I think it's 9.6MHz * Double data rate factor.
but if you can vary the clock now you'd need to use the max clock before using BRA/BPT...

@plbossart I think it is the sampling rate of the HDA stream. But I am not sure how does it related to the SoundWire bus rate. The SDW bus clock and the HDA sampling rate seems to be independent to me.
I guess why 192000 is because that is the max value of rate_bits[].

plbossart · 2025-01-07T19:45:31Z

sound/soc/sof/intel/hda-sdw-bpt.c

+							  false);
+		msleep(1);
+		i++;
+	} while (tx_position && i < HDA_BPT_IOC_TIMEOUT_MS);


probably need an error message if the DMA position was never cleared and the timeout happens?

plbossart · 2025-01-07T19:46:14Z

sound/soc/sof/intel/hda-sdw-bpt.c

+							  false);
+		msleep(1);
+		i++;
+	} while (rx_position && i < HDA_BPT_IOC_TIMEOUT_MS);


same comment on error message on timeout

plbossart · 2025-01-07T19:47:36Z

sound/soc/sof/intel/hda-sdw-bpt.c

+
+	ret1 = hda_sdw_bpt_dma_disable(dev, bpt_tx_stream);
+	if (!ret)
+		ret = ret1;


I can't remember if there's any reason to disable RX first?

I think it is because we enable TX first. So to be symmetrical, we disable RX first.

The Bulk Register Access protocol was left as a TODO topic since 2018. It's time to document this protocol and the design of its Linux support. Signed-off-by: Pierre-Louis Bossart <[email protected]>

The register definitions are missing a BULK_ENABLE bitfield which must be set for DP0. In addition, the existing mapping from PDI to Data Port is 1:1. That's fine for PCM streams which are by construction in one direction only. The BTP/BRA protocol is bidirectional and relies on DP0 only, which breaks the 1:1 mapping. DP0 MUST be mapped to both PDI0 and PDI1, with PDI0 taking care of the TX direction and PDI1 of the RX direction. Signed-off-by: Pierre-Louis Bossart <[email protected]>

In the existing definition of sdw_stream_runtime, the 'type' member is never set and defaults to PCM. To prepare for the BPT/BRA support, we need to special-case streams and make use of the 'type'. No functional change for now, the implicit PCM type is now explicit. Signed-off-by: Pierre-Louis Bossart <[email protected]>

BPT/BRA need to be special cased, i.e. there's no point in using the bandwidth allocation since the entire frame can be used. Signed-off-by: Pierre-Louis Bossart <[email protected]>

For BPT support, we want to allocate the entire audio payload and bypass the allocation based on PCM/PDM parameters. Signed-off-by: Pierre-Louis Bossart <[email protected]>

DP0 (Data Port 0) is very similar to regular data ports, with minor tweaks we can reuse the same code. Signed-off-by: Pierre-Louis Bossart <[email protected]>

Add definitions and helpers for the BPT/BRA protocol. Peripheral drivers (aka ASoC codec drivers) can use this API to send bulk data such as firmware or tables. The design intent is however NOT to directly use this API but to rely on an intermediate regmap layer. The API is only available when no other audio streams have been allocated, and only one BTP/BRA stream is allowed per link. To avoid the addition of yet another lock, the refcount tests are handled in the stream master_runtime alloc/free routines where the bus_lock is already held. Another benefit of this approach is that the same bus_lock is used to handle runtime and port linked lists, which reduces the potential for misaligned configurations. In addition to exclusion with audio streams, BPT transfers have a lot of overhead, specifically registers writes are needed to enable transport in DP0. Most DMAs don't handle too well very small data sets and they may have alignment limitations. The size and alignment requirements are for now not handled by the core but must be checked by platform-specific drivers. Signed-off-by: Pierre-Louis Bossart <[email protected]>

Add a convenience pointer to the 'sdw_bus' structure. BPT is a dedicated stream which will typically not be handled by DAIs or dailinks. Since there's only one BPT stream per link, storing the pointer at the link level seems rather natural. Signed-off-by: Pierre-Louis Bossart <[email protected]>

The Cadence IP expects a specific format (detailed in the Documentation). Add helpers to copy the data into the DMA buffer. The crc8 table is for now only used by the Cadence driver. This table might be moved to a common module at a later point if needed by other controller implementations. Signed-off-by: Pierre-Louis Bossart <[email protected]>

Mirror abstraction added for master ops. Signed-off-by: Pierre-Louis Bossart <[email protected]>

lgirdwood · 2025-01-08T16:54:23Z

@ujfalusi can you give this a review too. Thanks !

sound/soc/sof/intel/hda-sdw-bpt.c

Add SoundWire BPT DMA helpers as a separate module to avoid circular dependencies. For now this assumes no link DMA, only coupled mode. Signed-off-by: Pierre-Louis Bossart <[email protected]>

This is needed to be shared between open/send_async/close. Signed-off-by: Pierre-Louis Bossart <[email protected]>

Add support for BTP API using Cadence and hda-sdw-bpt helpers. Signed-off-by: Pierre-Louis Bossart <[email protected]>

Add code to show what codec drivers will need to do to enable BPT/BRA transfers. The only difference is to set the 'command_type' file to '1'. A zero-value will rely on regular read/write commands in Column0. Signed-off-by: Pierre-Louis Bossart <[email protected]>

DP0 is required for BPT/BRA transport. Signed-off-by: Pierre-Louis Bossart <[email protected]>

When the firmware is involved, the data can be transferred with a CHAIN_DMA on LNL+. The CHAIN_DMA needs to be programmed before the DMAs per the documentation. The states are not exactly symmetrical, on stop we must do a PAUSE and RESET. The FIFO size of 10ms was determined experimentally. With the minimum of 2ms, errors were reported by the codec, likely because of xruns. The code flow deals with the two TX and RX CHAIN_DMAs in symmetrical ways, i.e. alloc TX alloc RX enable TX enable RX disable RX disable TX free RX free TX Co-developed-by: Bard Liao <[email protected]> Signed-off-by: Bard Liao <[email protected]> Signed-off-by: Pierre-Louis Bossart <[email protected]>

bardliao force-pushed the sdw/start-BRA-support branch from 5d16674 to 1b0b781 Compare December 6, 2024 05:33

bardliao commented Dec 11, 2024

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bardliao commented Dec 11, 2024

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bardliao commented Dec 12, 2024

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bardliao commented Dec 12, 2024

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bardliao commented Dec 12, 2024

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bardliao force-pushed the sdw/start-BRA-support branch from 1b0b781 to 336a2f4 Compare December 24, 2024 07:44

bardliao force-pushed the sdw/start-BRA-support branch 4 times, most recently from 4291dd7 to 1eb379b Compare January 6, 2025 12:32

bardliao marked this pull request as ready for review January 6, 2025 12:55

bardliao requested review from lgirdwood, plbossart, ranj063, kv2019i, dbaluta and ujfalusi as code owners January 6, 2025 12:55

ranj063 reviewed Jan 6, 2025

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bardliao force-pushed the sdw/start-BRA-support branch from 1eb379b to 8debac1 Compare January 7, 2025 07:47

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plbossart reviewed Jan 7, 2025

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bardliao force-pushed the sdw/start-BRA-support branch from 8debac1 to 470fcc9 Compare January 8, 2025 03:55

plbossart added 6 commits January 8, 2025 16:50

Documentation: driver: add SoundWire BRA description

88968fe

The Bulk Register Access protocol was left as a TODO topic since 2018. It's time to document this protocol and the design of its Linux support. Signed-off-by: Pierre-Louis Bossart <[email protected]>

soundwire: extend sdw_stream_type to BPT

b426e23

BPT/BRA need to be special cased, i.e. there's no point in using the bandwidth allocation since the entire frame can be used. Signed-off-by: Pierre-Louis Bossart <[email protected]>

soundwire: stream: special-case the bus compute_params() routine

e0d72da

For BPT support, we want to allocate the entire audio payload and bypass the allocation based on PCM/PDM parameters. Signed-off-by: Pierre-Louis Bossart <[email protected]>

soundwire: stream: reuse existing code for BPT stream

2bb518d

DP0 (Data Port 0) is very similar to regular data ports, with minor tweaks we can reuse the same code. Signed-off-by: Pierre-Louis Bossart <[email protected]>

plbossart added 4 commits January 8, 2025 16:50

soundwire: intel_auxdevice: add indirection for BPT send_async/wait

6eb1525

Mirror abstraction added for master ops. Signed-off-by: Pierre-Louis Bossart <[email protected]>

bardliao force-pushed the sdw/start-BRA-support branch from 470fcc9 to fa54048 Compare January 8, 2025 08:51

ranj063 reviewed Jan 8, 2025

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sound/soc/sof/intel/hda-sdw-bpt.c Show resolved Hide resolved

plbossart added 6 commits January 9, 2025 10:53

ASoC: SOF: Intel: hda-sdw-bpt: add helpers for SoundWire BPT DMA

533a76b

Add SoundWire BPT DMA helpers as a separate module to avoid circular dependencies. For now this assumes no link DMA, only coupled mode. Signed-off-by: Pierre-Louis Bossart <[email protected]>

soundwire: intel: add BPT context definition

0dcb824

This is needed to be shared between open/send_async/close. Signed-off-by: Pierre-Louis Bossart <[email protected]>

soundwire: intel_ace2x: add BPT send_async/wait callbacks

d81ae8f

Add support for BTP API using Cadence and hda-sdw-bpt helpers. Signed-off-by: Pierre-Louis Bossart <[email protected]>

ASoC: rt711-sdca: add DP0 support

ab140ef

DP0 is required for BPT/BRA transport. Signed-off-by: Pierre-Louis Bossart <[email protected]>

bardliao force-pushed the sdw/start-BRA-support branch from fa54048 to dc995f8 Compare January 9, 2025 03:11

ranj063 approved these changes Jan 9, 2025

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SoundWire: start adding BPT/BRA support #5266

SoundWire: start adding BPT/BRA support #5266

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lgirdwood commented Jan 8, 2025



		(2) Multiple data lane support.
		(1) Multiple data lane support.

SoundWire: start adding BPT/BRA support #5266

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SoundWire: start adding BPT/BRA support #5266

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lgirdwood commented Jan 8, 2025