arch/arm64/imx9: Add trdc support

arch/arm64/src/imx9/Kconfig

@@ -58,6 +58,7 @@ config IMX9_HAVE_ATF_FIRMWARE
 config IMX9_BOOTLOADER
 	bool "Bootloader"
 	select ARM64_DECODEFIQ
+	select IMX9_DDR_TRAINING
 	default n
 	---help---
 		Configure NuttX as the bootloader. NuttX will be compiled
@@ -71,6 +72,13 @@ config BOOTLOADER_SYS_CLOCK
 		If the sysclk is set to a certain value, this should be it.
 		The value is used by the timer interrupt infrastructure.
 
+config IMX9_DDR_TRAINING
+	bool "DDR Training"
+	depends on IMX9_BOOTLOADER
+	default n
+	---help---
+		Perform DDR training to prepare the external memory for use.
+
 menu "i.MX9 Peripheral Selection"
 
 config IMX9_EDMA

arch/arm64/src/imx9/Make.defs

@@ -77,5 +77,6 @@ ifeq ($(CONFIG_IMX9_FLEXSPI_NOR), y)
 endif
 
 ifeq ($(CONFIG_IMX9_BOOTLOADER), y)
-  CHIP_CSRCS += imx9_system_ctl.c
+ CHIP_CSRCS += imx9_system_ctl.c
+ CHIP_CSRCS += imx9_trdc.c
 endif

arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h

@@ -105,6 +105,7 @@
 #define IMX9_MU1__MUB_BASE                 (0x44230000UL)
 #define IMX9_MU2__MUB_BASE                 (0x42440000UL)
 #define IMX9_S3MUA_BASE                    (0x47520000UL)
+#define IMX9_TRDC_BASE                     (0x49010000UL)
 #define IMX9_NPU_BASE                      (0x4A900000UL)
 #define IMX9_OCOTP_BASE                    (0x47518000UL)
 #define IMX9_OCRAM_MECC1_BASE              (0x490A0000UL)

arch/arm64/src/imx9/hardware/imx9_trdc.h

@@ -0,0 +1,97 @@
+/****************************************************************************
+ * arch/arm64/src/imx9/hardware/imx9_trdc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_TRDC_H
+#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_TRDC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/imx9_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define IMX9_TRDC_HWCFG0        (IMX9_TRDC_BASE + 0xf0)
+
+#define IMX9_MBC0_MEM_GLBAC(n)  (0x20 + (n << 2))
+#define IMX9_MBC_MEM_BLK_CFG_0(m, n)    (0x200 * m + 0x40 + (n << 2))
+#define IMX9_MBC_MEM_BLK_CFG_I(m, n, i) (0x200 * m + 0x40 + (80 << 2) + (i - 1) * 0x28 + (n << 2))
+#define IMX9_MRC0_DOM_RGD_W(m, n)       (0x100 * m + 0x40 + (n << 3))
+
+#define ELE_MAX_MSG 255U
+#define AHAB_VERSION 0x6
+#define AHAB_CMD_TAG 0x17
+#define AHAB_RESP_TAG 0xe1
+#define ELE_RELEASE_RDC_REQ (0xC4)
+#define ELE_READ_FUSE_REQ	  (0x97)
+#define ELE_OK            0xd6
+
+#define FSB_BASE			0x47510000UL
+#define FSB_SHADOW_OFF		0x8000UL
+
+#define BLK_CTRL_NS_ANOMIX_BASE  IMX9_BLK_CTRL_NS_AONMIX1_BASE
+
+#define ELE_MU_TCR	(IMX9_S3MUA_BASE+ 0x120)
+#define ELE_MU_TSR	(IMX9_S3MUA_BASE+ 0x124)
+#define ELE_MU_RCR	(IMX9_S3MUA_BASE+ 0x128)
+#define ELE_MU_RSR	(IMX9_S3MUA_BASE+ 0x12c)
+
+#define ELE_RR_NUM        4
+#define ELE_TR_NUM        8
+#define ELE_MU_TR(i)	(IMX9_S3MUA_BASE + 0x200 + (i) * 4)
+#define ELE_MU_RR(i)	(IMX9_S3MUA_BASE + 0x280 + (i) * 4)
+
+#define DID_NUM 16
+#define MBC_MAX_NUM 4
+#define MRC_MAX_NUM 2
+#define MBC_NUM(HWCFG) ((HWCFG >> 16) & 0xF)
+#define MRC_NUM(HWCFG) ((HWCFG >> 24) & 0x1F)
+
+#define MBC_BLK_NUM(GLBCFG) (GLBCFG & 0x3FF)
+#define MRC_RGN_NUM(GLBCFG) (GLBCFG & 0x1F)
+
+#define GLBAC_SETTING_MASK	(0x7777)
+#define GLBAC_LOCK_MASK	BIT(31)
+
+struct ele_header_t
+{
+  union
+    {
+      uint32_t data;
+      struct
+        {
+          uint32_t version : 8;
+          uint32_t size : 8;
+          uint32_t command : 8;
+          uint32_t tag : 8;
+        };
+    };
+};
+
+struct ele_msg
+{
+  struct ele_header_t header;
+  uint32_t data[(ELE_MAX_MSG - 1)];
+};
+
+#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_TRDC_H */

arch/arm64/src/imx9/imx9_boot.c

@@ -40,6 +40,8 @@
 
 #include "imx9_boot.h"
 #include "imx9_clockconfig.h"
+#include "imx9_ccm.h"
+#include "imx9_trdc.h"
 #include "imx9_serial.h"
 #include "imx9_gpio.h"
 #include "imx9_lowputc.h"
@@ -58,9 +60,11 @@ static const struct arm_mmu_region g_mmu_regions[] =
                         CONFIG_RAMBANK1_ADDR, CONFIG_RAMBANK1_SIZE,
                         MT_NORMAL | MT_RW | MT_SECURE),
 
+#ifndef CONFIG_IMX9_DDR_TRAINING /* OCRAM set at arm64_mmu.c */
   MMU_REGION_FLAT_ENTRY("OCRAM",
                         CONFIG_OCRAM_BASE_ADDR, CONFIG_OCRAM_SIZE,
                         MT_NORMAL | MT_RW | MT_SECURE),
+#endif
 
   MMU_REGION_FLAT_ENTRY("FSPI_PERIPHERAL",
                         CONFIG_FSPI_PER_BASEADDR, CONFIG_FSPI_PER_SIZE,
@@ -116,15 +120,20 @@ void arm64_chip_boot(void)
 {
 #ifdef CONFIG_IMX9_BOOTLOADER
   imx9_mix_powerup();
-#endif
-  /* MAP IO and DRAM, enable MMU. */
 
-  arm64_mmu_init(true);
+  /* Before DDR init we need to initialize clocks and trdc */
+
+  imx9_ccm_clock_init();
 
-  /* Initialize system clocks to some sensible state */
+  imx9_trdc_init();
 
   imx9_clockconfig();
 
+#endif
+  /* MAP IO and DRAM, enable MMU. */
+
+  arm64_mmu_init(true);
+
   /* Do UART early initialization & pin muxing */
 #ifdef CONFIG_IMX9_LPUART
   imx9_lowsetup();