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Summer 2023 "Add features" release
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@tomcl tomcl released this 11 Jul 16:02
· 250 commits to master since this release
v4.0.a.14
d3c08d3

This is the alpha release of Issie with improvements from 2023 work. It is slightly less stable than Issie normally, but mainly is alpha because it is expected that new features from 2023 work will continue to be added over the Summer.

Binaries will be updated on this release, with new tags, till Issie is ready for the Autumn Term v4.1.0 production release. (NB binaries will be labelled 4.0.1 etc because 4.0.a.1 is not allowed - however Issie versions will be correct).

v4.0.a.14

  1. Many UI improvements and bug fixes throughout
  2. Web workers added and tested - but not yet used.
  3. Built-in demo designs added

v4.0.a.13

  1. fix Ctrl-W so it always works changing sheets
  2. Misc UI improvements, tooltips, responsiveness.
  3. Reduce unnecessary saving of sheets.

v4.0.a.12

  1. Various fixes to multi-symbol rotate and scale
  2. fix obscure bug in separation code
  3. reduce separation so circuits do not need saving immediately after load

v4.0.a.11

  1. Replace sheets menu by new breadcrumbs hierarchy with right-click ops.

v4.0.a.10

  1. Added 3 & 4 input gates
  2. Added "add sheet" function (NB some improvement is still expected for complex cases)
  3. Added right-click context menus to draw block objects

Fixes:

  • Custom symbol size change

v4.0.a.9

  1. Increase default wire separation
  2. Fix bug when dragging segments

v4.0.a.8

  1. improve separation: do not separate close same-net segments
  2. When dragging multiple segments, all segments move together

v4.0.a.7

  1. Fix top-level rerouting command

v4.0.a.6

  1. Various improvements to separation - it should now be almost perfect
  2. Edit menu commands to invoke reseparation, or autoroute and separation.

v4.0.a.5

  1. Fix squiggly wire artifacts in new-style wire routing and separation
  2. Fix N-bit NOT display bug
  3. Add hint to custom component port movement and scaling ops
  4. Various small fixes

v4.0.a.4

  1. Fix a serious bug preventing IOLabel from simulating which was introduced by 338f4b1

v4.0.a.3 --- Contains IOLabel simulation bug - don't use

  1. Add "not connected" component
  2. Mend simulator bug regression introduced by fdd56a7

v4.0.a.2 --- Contains IOLabel simulation bug - don't use

  1. Lots of internal changes
  2. Make truth tables work
  3. Verilog compiler + components added

v4.0.a.1

  1. Add new (better) wire routing.
  2. Add wire separation
  3. Add multi-symbol scale and rotate
Assets 4
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